139 lines
4.1 KiB
C
139 lines
4.1 KiB
C
/*******************************************************************************
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Intel SmartPHY DSL PCIe Endpoint/ACA Linux driver
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Copyright(c) 2016 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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*******************************************************************************/
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#ifndef REGS_H
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#define REGS_H
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#include <linux/bitops.h>
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/* APPL defined */
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#define PCIE_APPL_BASE 0x00048000
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#define PCIE_APPL_REG(X) (PCIE_APPL_BASE + (X))
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#define PCIE_APPL_PHY_CFG1 PCIE_APPL_REG(0x3C)
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#define PCIE_APPL_PHY_CFG2 PCIE_APPL_REG(0x40)
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#define PCIE_APPL_PHY_CFG3 PCIE_APPL_REG(0x58)
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#define PCIE_APPL_PHY_CFG4 PCIE_APPL_REG(0x28)
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#define PCIE_APPL_INTR_VEC PCIE_APPL_REG(0x48)
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#define PCIE_APPL_MSI_EN PCIE_APPL_REG(0x4C)
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#define PCIE_MSI_EN_ALL 0xFF
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/* RCU defined */
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#define RCU_BASE 0x00008000
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#define RCU_REG(X) (RCU_BASE + (X))
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#define RCU_STAT RCU_REG(0x00)
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#define RCU_REQ RCU_REG(0x10)
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#define RCU_MSI RCU_REG(0x80)
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#define PCI_MSI_4_MODE 1
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#define PCI_MSI_8_MODE 0
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/* CGU */
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#define CGU_BASE 0x00000000
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#define CGU_REG(X) (CGU_BASE + (X))
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#define PMU_PWDCR CGU_REG(0x011C)
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#define PMU_SR CGU_REG(0x0120)
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#define PMU_ALL 0x20ec0305
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#define PLL_OMCFG CGU_REG(0x0064)
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#define SYS_CLK 0x3
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#define SYS_CLK_S 0
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#define PPE_CLK 0x700
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#define PPE_CLK_S 8
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#define IF_CLK CGU_REG(0x0024)
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#define CLK_PD BIT(10)
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#define CLK_OD BIT(11)
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#define PCIE_CLKOD (BIT(12) | BIT(13))
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#define AFE_CLKOD BIT(14)
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#define IF_CLKOD_ALL (CLK_PD | CLK_OD | PCIE_CLKOD | AFE_CLKOD)
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/* GPIO */
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#define GPIO_BASE 0x00020000
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#define GPIO_REG(X) (GPIO_BASE + (X))
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#define GPIO_OUT GPIO_REG(0x00)
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#define GPIO_IN GPIO_REG(0x04)
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#define GPIO_DIR GPIO_REG(0x08)
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#define GPIO_OUTSET GPIO_REG(0x40)
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#define GPIO_OUTCLR GPIO_REG(0x44)
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#define GPIO_DIRSET GPIO_REG(0x48)
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#define GPIO_DIRCLR GPIO_REG(0x4c)
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/* PADC */
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#define PADC_BASE 0x00024000
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#define PADC_REG(X) (PADC_BASE + (X))
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#define PADC_MUX(pin) PADC_REG(((pin) << 2))
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#define PADC_PUEN PADC_REG(0x80)
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#define PADC_PDEN PADC_REG(0x84)
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#define PADC_SRC PADC_REG(0x88)
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#define PADC_DCC PADC_REG(0x8c)
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#define PADC_OD PADC_REG(0x94)
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#define PADC_AVAIL PADC_REG(0x98)
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#define PADC_MUX_M 0x7
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/* ICU defined */
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#define ICU_BASE 0x00010000
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#define ICU_REG(X) (ICU_BASE + (X))
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#define ICU_IMSR ICU_REG(0x40)
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#define ICU_IMER ICU_REG(0x44)
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#define ICU_IMOSR ICU_REG(0x48)
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#define ICU_DMA_TX_STATUS ICU_REG(0x50)
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#define ICU_DMA_RX_STATUS ICU_REG(0x54)
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#define ICU_DMA_TX_IMER ICU_REG(0x58)
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#define ICU_DMA_RX_IMER ICU_REG(0x5C)
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#define ICU_DMA_TX_IMOSR ICU_REG(0x60)
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#define ICU_DMA_RX_IMOSR ICU_REG(0x64)
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#define PPE2HOST_INT0 BIT(0)
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#define PPE2HOST_INT1 BIT(1)
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#define DYING_GASP_INT BIT(3)
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#define MEI_IRQ BIT(8)
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#define ACA_XBAR_INT BIT(9)
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#define MODEM_XBAR_INT BIT(12)
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#define LED0_INT BIT(13)
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#define LED1_INT BIT(14)
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#define NMI_PLL BIT(15)
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#define DMA_TX BIT(16)
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#define DMA_RX BIT(17)
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#define ACA_HOSTIF_TX BIT(20)
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#define ACA_HOSTIF_RX BIT(21)
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#define ACA_RXOUT_PD_RING_FULL BIT(22)
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#define ACA_TXOUT_PD_RING_FULL BIT(23)
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#define ICU_TOP_ALL 0x0003f30B /* Except ACA related */
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#define ICU_DMA_TX_ALL 0x003f03FF
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#define ICU_DMA_RX_ALL 0x003F03FF
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#define wr32(value, reg) (writel(value, (priv->mem + (reg))))
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#define rd32(reg) (readl(priv->mem + (reg)))
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#define wrfl() ((void)rd32(RCU_STAT))
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#define wr32_mask(clr, set, reg) \
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wr32(((rd32(reg) & ~(clr)) | (set)), (reg))
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#endif /* REGS_H */
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