mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2024-12-13 10:24:51 +00:00
a2adeffffc
Refreshed all patches. Fixes CVE: - CVE-2018-7755 Compile-tested on: cns3xxx, imx6 Runtime-tested on: cns3xxx, imx6 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
124 lines
3.6 KiB
Diff
124 lines
3.6 KiB
Diff
From d31800ff6ed81f44488b590fe372e7b6572d2896 Mon Sep 17 00:00:00 2001
|
|
From: Kristian Evensen <kristian.evensen@gmail.com>
|
|
Date: Sun, 17 Jun 2018 14:18:45 +0200
|
|
Subject: [PATCH] arm: dts: Add missing mt7623 pcie nodes
|
|
|
|
---
|
|
arch/arm/boot/dts/mt7623.dtsi | 105 ++++++++++++++++++++++++++++++++++++++++++
|
|
1 file changed, 105 insertions(+)
|
|
|
|
--- a/arch/arm/boot/dts/mt7623.dtsi
|
|
+++ b/arch/arm/boot/dts/mt7623.dtsi
|
|
@@ -674,6 +674,111 @@
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
+ pcie: pcie@1a140000 {
|
|
+ compatible = "mediatek,mt7623-pcie";
|
|
+ device_type = "pci";
|
|
+ reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
|
|
+ <0 0x1a142000 0 0x1000>, /* Port0 registers */
|
|
+ <0 0x1a143000 0 0x1000>, /* Port1 registers */
|
|
+ <0 0x1a144000 0 0x1000>; /* Port2 registers */
|
|
+ reg-names = "subsys", "port0", "port1", "port2";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0xf800 0 0 0>;
|
|
+ interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
|
|
+ <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
|
|
+ <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
|
|
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
|
|
+ <&hifsys CLK_HIFSYS_PCIE0>,
|
|
+ <&hifsys CLK_HIFSYS_PCIE1>,
|
|
+ <&hifsys CLK_HIFSYS_PCIE2>;
|
|
+ clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
|
|
+ resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
|
|
+ <&hifsys MT2701_HIFSYS_PCIE1_RST>,
|
|
+ <&hifsys MT2701_HIFSYS_PCIE2_RST>;
|
|
+ reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
|
|
+ phys = <&pcie0_port PHY_TYPE_PCIE>,
|
|
+ <&pcie1_port PHY_TYPE_PCIE>,
|
|
+ <&u3port1 PHY_TYPE_PCIE>;
|
|
+ phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
|
|
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
|
|
+ bus-range = <0x00 0xff>;
|
|
+ status = "disabled";
|
|
+ ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
|
|
+ 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
|
|
+
|
|
+ pcie@0,0 {
|
|
+ reg = <0x0000 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
|
|
+ ranges;
|
|
+ num-lanes = <1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ pcie@1,0 {
|
|
+ reg = <0x0800 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
|
|
+ ranges;
|
|
+ num-lanes = <1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@2,0 {
|
|
+ reg = <0x1000 0 0 0 0>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 0>;
|
|
+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
|
|
+ ranges;
|
|
+ num-lanes = <1>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pcie0_phy: pcie-phy@1a149000 {
|
|
+ compatible = "mediatek,generic-tphy-v1";
|
|
+ reg = <0 0x1a149000 0 0x0700>;
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ pcie0_port: pcie-phy@1a149900 {
|
|
+ reg = <0 0x1a149900 0 0x0700>;
|
|
+ clocks = <&clk26m>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <1>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pcie1_phy: pcie-phy@1a14a000 {
|
|
+ compatible = "mediatek,generic-tphy-v1";
|
|
+ reg = <0 0x1a14a000 0 0x0700>;
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ pcie1_port: pcie-phy@1a14a900 {
|
|
+ reg = <0 0x1a14a900 0 0x0700>;
|
|
+ clocks = <&clk26m>;
|
|
+ clock-names = "ref";
|
|
+ #phy-cells = <1>;
|
|
+ status = "okay";
|
|
+ };
|
|
+ };
|
|
+
|
|
+
|
|
usb1: usb@1a1c0000 {
|
|
compatible = "mediatek,mt7623-xhci",
|
|
"mediatek,mt8173-xhci";
|