mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2024-12-13 10:24:51 +00:00
6cd41b419c
Refreshed all patches. Compile-tested on: cns3xxx, imx6 Runtime-tested on: cns3xxx, imx6 Fixes for CVEs: CVE-2018-1108 CVE-2018-1092 CVE-2018-1094 CVE-2018-1095 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com> Tested-by: Stijn Segers <foss@volatilesystems.org>
28 lines
969 B
Diff
28 lines
969 B
Diff
From 596c3a7300c0419dba71d58cbd4136e0d1e12a4e Mon Sep 17 00:00:00 2001
|
|
From: Shunli Wang <shunli.wang@mediatek.com>
|
|
Date: Tue, 5 Jan 2016 14:30:22 +0800
|
|
Subject: [PATCH 06/57] reset: mediatek: mt2701 reset driver
|
|
|
|
In infrasys and perifsys, there are many reset
|
|
control bits for kinds of modules. These bits are
|
|
used as actual reset controllers to be registered
|
|
into kernel's generic reset controller framework.
|
|
|
|
Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
|
|
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
|
|
---
|
|
drivers/clk/mediatek/clk-mt2701.c | 4 ++++
|
|
1 file changed, 4 insertions(+)
|
|
|
|
--- a/drivers/clk/mediatek/clk-mt2701.c
|
|
+++ b/drivers/clk/mediatek/clk-mt2701.c
|
|
@@ -772,6 +772,8 @@ static void mtk_infrasys_init_early(stru
|
|
if (r)
|
|
pr_err("%s(): could not register clock provider: %d\n",
|
|
__func__, r);
|
|
+
|
|
+ mtk_register_reset_controller(node, 2, 0x30);
|
|
}
|
|
CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
|
|
mtk_infrasys_init_early);
|