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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
41 lines
1.4 KiB
Diff
41 lines
1.4 KiB
Diff
From 0311903940046649e20bd23bca837169eb4525dc Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 16 Nov 2022 22:48:41 +0100
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Subject: [PATCH] arm64: dts: qcom: ipq8074: correct PCIe QMP PHY output clock
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names
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Current PCIe QMP PHY output name were changed in ("arm64: dts: qcom: Fix
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IPQ8074 PCIe PHY nodes") however it did not account for the fact that GCC
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driver is relying on the old names to match them as they are being used as
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the parent for the gcc_pcie0_pipe_clk and gcc_pcie1_pipe_clk.
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This broke parenting as GCC could not find the parent clock, so fix it by
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changing to the names that driver is expecting.
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Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes")
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -257,7 +257,7 @@
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#clock-cells = <0>;
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clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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clock-names = "pipe0";
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- clock-output-names = "pcie_0_pipe_clk";
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+ clock-output-names = "pcie20_phy0_pipe_clk";
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};
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};
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@@ -285,7 +285,7 @@
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#clock-cells = <0>;
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clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
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clock-names = "pipe0";
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- clock-output-names = "pcie_1_pipe_clk";
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+ clock-output-names = "pcie20_phy1_pipe_clk";
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};
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};
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