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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
123 lines
4.0 KiB
Diff
123 lines
4.0 KiB
Diff
From 180ce25d5c3ccff206f084b7ab350778641d1b1c Mon Sep 17 00:00:00 2001
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From: Prasad Malisetty <pmaliset@codeaurora.org>
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Date: Thu, 7 Oct 2021 23:18:42 +0530
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Subject: [PATCH] PCI: qcom: Replace ops with struct pcie_cfg in pcie match
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data
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Add struct qcom_pcie_cfg as match data for all platforms. Assign
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appropriate platform ops into struct qcom_pcie_cfg and read using
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of_device_get_match_data() in qcom_pcie_probe().
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Link: https://lore.kernel.org/r/1633628923-25047-5-git-send-email-pmaliset@codeaurora.org
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Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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---
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drivers/pci/controller/dwc/pcie-qcom.c | 66 +++++++++++++++++++++-----
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1 file changed, 55 insertions(+), 11 deletions(-)
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -202,6 +202,10 @@ struct qcom_pcie_ops {
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int (*config_sid)(struct qcom_pcie *pcie);
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};
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+struct qcom_pcie_cfg {
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+ const struct qcom_pcie_ops *ops;
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+};
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+
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struct qcom_pcie {
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struct dw_pcie *pci;
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void __iomem *parf; /* DT parf */
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@@ -1469,6 +1473,38 @@ static const struct qcom_pcie_ops ops_1_
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.config_sid = qcom_pcie_config_sid_sm8250,
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};
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+static const struct qcom_pcie_cfg apq8084_cfg = {
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+ .ops = &ops_1_0_0,
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+};
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+
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+static const struct qcom_pcie_cfg ipq8064_cfg = {
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+ .ops = &ops_2_1_0,
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+};
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+
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+static const struct qcom_pcie_cfg msm8996_cfg = {
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+ .ops = &ops_2_3_2,
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+};
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+
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+static const struct qcom_pcie_cfg ipq8074_cfg = {
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+ .ops = &ops_2_3_3,
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+};
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+
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+static const struct qcom_pcie_cfg ipq4019_cfg = {
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+ .ops = &ops_2_4_0,
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+};
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+
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+static const struct qcom_pcie_cfg sdm845_cfg = {
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+ .ops = &ops_2_7_0,
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+};
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+
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+static const struct qcom_pcie_cfg sm8250_cfg = {
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+ .ops = &ops_1_9_0,
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+};
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+
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+static const struct qcom_pcie_cfg sc7280_cfg = {
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+ .ops = &ops_1_9_0,
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+};
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+
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static const struct dw_pcie_ops dw_pcie_ops = {
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.link_up = qcom_pcie_link_up,
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.start_link = qcom_pcie_start_link,
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@@ -1480,6 +1516,7 @@ static int qcom_pcie_probe(struct platfo
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struct pcie_port *pp;
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struct dw_pcie *pci;
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struct qcom_pcie *pcie;
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+ const struct qcom_pcie_cfg *pcie_cfg;
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int ret;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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@@ -1501,7 +1538,13 @@ static int qcom_pcie_probe(struct platfo
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pcie->pci = pci;
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- pcie->ops = of_device_get_match_data(dev);
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+ pcie_cfg = of_device_get_match_data(dev);
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+ if (!pcie_cfg || !pcie_cfg->ops) {
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+ dev_err(dev, "Invalid platform data\n");
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+ return -EINVAL;
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+ }
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+
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+ pcie->ops = pcie_cfg->ops;
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pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
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if (IS_ERR(pcie->reset)) {
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@@ -1557,16 +1600,17 @@ err_pm_runtime_put:
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}
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static const struct of_device_id qcom_pcie_match[] = {
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- { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
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- { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
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- { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
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- { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
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- { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
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- { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
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- { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
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- { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
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- { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
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- { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 },
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+ { .compatible = "qcom,pcie-apq8084", .data = &apq8084_cfg },
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+ { .compatible = "qcom,pcie-ipq8064", .data = &ipq8064_cfg },
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+ { .compatible = "qcom,pcie-ipq8064-v2", .data = &ipq8064_cfg },
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+ { .compatible = "qcom,pcie-apq8064", .data = &ipq8064_cfg },
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+ { .compatible = "qcom,pcie-msm8996", .data = &msm8996_cfg },
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+ { .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
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+ { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
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+ { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
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+ { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
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+ { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
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+ { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
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{ }
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};
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