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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
95 lines
2.7 KiB
Diff
95 lines
2.7 KiB
Diff
From a9ab8f5de2fc752e37918cfd5dcd16d625d9ecb2 Mon Sep 17 00:00:00 2001
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From: Shawn Guo <shawn.guo@linaro.org>
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Date: Wed, 29 Sep 2021 11:42:51 +0800
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Subject: [PATCH] arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes
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IPQ8074 PCIe PHY nodes are broken in the many ways:
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- '#address-cells', '#size-cells' and 'ranges' are missing.
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- Child phy/lane node is missing, and the child properties like
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'#phy-cells' and 'clocks' are mistakenly put into parent node.
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- The clocks properties for parent node are missing.
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Fix them to get the nodes comply with the bindings schema.
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20210929034253.24570-9-shawn.guo@linaro.org
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 46 +++++++++++++++++++++------
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1 file changed, 36 insertions(+), 10 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -174,34 +174,60 @@
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status = "disabled";
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};
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- pcie_phy0: phy@86000 {
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+ pcie_qmp0: phy@86000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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reg = <0x00086000 0x1000>;
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- #phy-cells = <0>;
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- clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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- clock-names = "pipe_clk";
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- clock-output-names = "pcie20_phy0_pipe_clk";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ clocks = <&gcc GCC_PCIE0_AUX_CLK>,
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+ <&gcc GCC_PCIE0_AHB_CLK>;
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+ clock-names = "aux", "cfg_ahb";
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resets = <&gcc GCC_PCIE0_PHY_BCR>,
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<&gcc GCC_PCIE0PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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status = "disabled";
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+
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+ pcie_phy0: phy@86200 {
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+ reg = <0x86200 0x16c>,
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+ <0x86400 0x200>,
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+ <0x86800 0x4f4>;
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+ #phy-cells = <0>;
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+ #clock-cells = <0>;
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+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
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+ clock-names = "pipe0";
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+ clock-output-names = "pcie_0_pipe_clk";
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+ };
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};
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- pcie_phy1: phy@8e000 {
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+ pcie_qmp1: phy@8e000 {
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compatible = "qcom,ipq8074-qmp-pcie-phy";
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reg = <0x0008e000 0x1000>;
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- #phy-cells = <0>;
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- clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
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- clock-names = "pipe_clk";
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- clock-output-names = "pcie20_phy1_pipe_clk";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ clocks = <&gcc GCC_PCIE1_AUX_CLK>,
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+ <&gcc GCC_PCIE1_AHB_CLK>;
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+ clock-names = "aux", "cfg_ahb";
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resets = <&gcc GCC_PCIE1_PHY_BCR>,
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<&gcc GCC_PCIE1PHY_PHY_BCR>;
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reset-names = "phy",
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"common";
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status = "disabled";
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+
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+ pcie_phy1: phy@8e200 {
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+ reg = <0x8e200 0x16c>,
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+ <0x8e400 0x200>,
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+ <0x8e800 0x4f4>;
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+ #phy-cells = <0>;
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+ #clock-cells = <0>;
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+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
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+ clock-names = "pipe0";
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+ clock-output-names = "pcie_1_pipe_clk";
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+ };
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};
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prng: rng@e3000 {
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