169 lines
4.7 KiB
Diff
169 lines
4.7 KiB
Diff
From f3eacff2310a60348a755c50a8da6fc251fc8587 Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Tue, 6 Mar 2018 09:55:13 +0100
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Subject: [PATCH 07/33] irqchip/irq-ath79-intc: add irq cascade driver for
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QCA9556 SoCs
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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drivers/irqchip/Makefile | 1 +
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drivers/irqchip/irq-ath79-intc.c | 142 +++++++++++++++++++++++++++++++++++++++
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2 files changed, 143 insertions(+)
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create mode 100644 drivers/irqchip/irq-ath79-intc.c
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--- a/drivers/irqchip/Makefile
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+++ b/drivers/irqchip/Makefile
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@@ -4,6 +4,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o
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obj-$(CONFIG_AL_FIC) += irq-al-fic.o
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obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
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obj-$(CONFIG_ATH79) += irq-ath79-cpu.o
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+obj-$(CONFIG_ATH79) += irq-ath79-intc.o
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obj-$(CONFIG_ATH79) += irq-ath79-misc.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
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--- /dev/null
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+++ b/drivers/irqchip/irq-ath79-intc.c
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@@ -0,0 +1,142 @@
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+/*
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+ * Atheros AR71xx/AR724x/AR913x specific interrupt handling
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+ *
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+ * Copyright (C) 2018 John Crispin <john@phrozen.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ */
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+
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+#include <linux/interrupt.h>
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+#include <linux/irqchip.h>
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+#include <linux/of.h>
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+#include <linux/of_irq.h>
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+#include <linux/irqdomain.h>
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+
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+#include <asm/irq_cpu.h>
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+#include <asm/mach-ath79/ath79.h>
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+#include <asm/mach-ath79/ar71xx_regs.h>
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+
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+#define ATH79_MAX_INTC_CASCADE 3
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+
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+struct ath79_intc {
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+ struct irq_chip chip;
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+ u32 irq;
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+ u32 pending_mask;
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+ u32 int_status;
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+ u32 irq_mask[ATH79_MAX_INTC_CASCADE];
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+ u32 irq_wb_chan[ATH79_MAX_INTC_CASCADE];
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+};
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+
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+static void ath79_intc_irq_handler(struct irq_desc *desc)
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+{
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+ struct irq_domain *domain = irq_desc_get_handler_data(desc);
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+ struct ath79_intc *intc = domain->host_data;
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+ u32 pending;
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+
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+ pending = ath79_reset_rr(intc->int_status);
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+ pending &= intc->pending_mask;
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+
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+ if (pending) {
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+ int i;
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+
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+ for (i = 0; i < domain->hwirq_max; i++)
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+ if (pending & intc->irq_mask[i]) {
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+ if (intc->irq_wb_chan[i] != 0xffffffff)
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+ ath79_ddr_wb_flush(intc->irq_wb_chan[i]);
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+ generic_handle_irq(irq_find_mapping(domain, i));
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+ }
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+ } else {
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+ spurious_interrupt();
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+ }
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+}
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+
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+static void ath79_intc_irq_enable(struct irq_data *d)
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+{
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+ struct ath79_intc *intc = d->domain->host_data;
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+ enable_irq(intc->irq);
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+}
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+
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+static void ath79_intc_irq_disable(struct irq_data *d)
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+{
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+ struct ath79_intc *intc = d->domain->host_data;
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+ disable_irq(intc->irq);
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+}
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+
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+static int ath79_intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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+{
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+ struct ath79_intc *intc = d->host_data;
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+
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+ irq_set_chip_and_handler(irq, &intc->chip, handle_level_irq);
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+
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+ return 0;
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+}
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+
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+static const struct irq_domain_ops ath79_irq_domain_ops = {
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+ .xlate = irq_domain_xlate_onecell,
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+ .map = ath79_intc_map,
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+};
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+
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+static int __init ath79_intc_of_init(
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+ struct device_node *node, struct device_node *parent)
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+{
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+ struct irq_domain *domain;
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+ struct ath79_intc *intc;
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+ int cnt, cntwb, i, err;
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+
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+ cnt = of_property_count_u32_elems(node, "qca,pending-bits");
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+ if (cnt > ATH79_MAX_INTC_CASCADE)
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+ panic("Too many INTC pending bits\n");
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+
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+ intc = kzalloc(sizeof(*intc), GFP_KERNEL);
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+ if (!intc)
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+ panic("Failed to allocate INTC memory\n");
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+ intc->chip = dummy_irq_chip;
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+ intc->chip.name = "INTC";
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+ intc->chip.irq_disable = ath79_intc_irq_disable;
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+ intc->chip.irq_enable = ath79_intc_irq_enable;
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+
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+ if (of_property_read_u32(node, "qca,int-status-addr", &intc->int_status) < 0) {
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+ panic("Missing address of interrupt status register\n");
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+ }
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+
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+ of_property_read_u32_array(node, "qca,pending-bits", intc->irq_mask, cnt);
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+ for (i = 0; i < cnt; i++) {
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+ intc->pending_mask |= intc->irq_mask[i];
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+ intc->irq_wb_chan[i] = 0xffffffff;
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+ }
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+
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+ cntwb = of_count_phandle_with_args(
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+ node, "qca,ddr-wb-channels", "#qca,ddr-wb-channel-cells");
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+
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+ for (i = 0; i < cntwb; i++) {
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+ struct of_phandle_args args;
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+ u32 irq = i;
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+
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+ of_property_read_u32_index(
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+ node, "qca,ddr-wb-channel-interrupts", i, &irq);
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+ if (irq >= ATH79_MAX_INTC_CASCADE)
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+ continue;
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+
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+ err = of_parse_phandle_with_args(
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+ node, "qca,ddr-wb-channels",
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+ "#qca,ddr-wb-channel-cells",
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+ i, &args);
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+ if (err)
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+ return err;
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+
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+ intc->irq_wb_chan[irq] = args.args[0];
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+ }
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+
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+ intc->irq = irq_of_parse_and_map(node, 0);
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+ if (!intc->irq)
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+ panic("Failed to get INTC IRQ");
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+
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+ domain = irq_domain_add_linear(node, cnt, &ath79_irq_domain_ops, intc);
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+ irq_set_chained_handler_and_data(intc->irq, ath79_intc_irq_handler, domain);
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+
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+ return 0;
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+}
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+IRQCHIP_DECLARE(ath79_intc, "qca,ar9340-intc",
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+ ath79_intc_of_init);
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