747 lines
22 KiB
Diff
747 lines
22 KiB
Diff
From patchwork Wed Nov 2 15:56:56 2016
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v9,1/3] clk: qcom: Add support for SMD-RPM Clocks
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From: Georgi Djakov <georgi.djakov@linaro.org>
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X-Patchwork-Id: 9409419
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Message-Id: <20161102155658.32203-2-georgi.djakov@linaro.org>
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To: sboyd@codeaurora.org, mturquette@baylibre.com
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Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
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robh+dt@kernel.org, mark.rutland@arm.com,
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linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
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georgi.djakov@linaro.org
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Date: Wed, 2 Nov 2016 17:56:56 +0200
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This adds initial support for clocks controlled by the Resource
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Power Manager (RPM) processor on some Qualcomm SoCs, which use
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the qcom_smd_rpm driver to communicate with RPM.
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Such platforms are msm8916, apq8084 and msm8974.
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The RPM is a dedicated hardware engine for managing the shared
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SoC resources in order to keep the lowest power profile. It
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communicates with other hardware subsystems via shared memory
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and accepts clock requests, aggregates the requests and turns
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the clocks on/off or scales them on demand.
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This driver is based on the codeaurora.org driver:
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https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c
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Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
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---
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.../devicetree/bindings/clock/qcom,rpmcc.txt | 36 ++
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drivers/clk/qcom/Kconfig | 16 +
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drivers/clk/qcom/Makefile | 1 +
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drivers/clk/qcom/clk-smd-rpm.c | 571 +++++++++++++++++++++
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include/dt-bindings/clock/qcom,rpmcc.h | 45 ++
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5 files changed, 669 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
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create mode 100644 drivers/clk/qcom/clk-smd-rpm.c
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create mode 100644 include/dt-bindings/clock/qcom,rpmcc.h
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--
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To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
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the body of a message to majordomo@vger.kernel.org
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More majordomo info at http://vger.kernel.org/majordomo-info.html
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
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@@ -0,0 +1,36 @@
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+Qualcomm RPM Clock Controller Binding
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+------------------------------------------------
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+The RPM is a dedicated hardware engine for managing the shared
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+SoC resources in order to keep the lowest power profile. It
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+communicates with other hardware subsystems via shared memory
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+and accepts clock requests, aggregates the requests and turns
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+the clocks on/off or scales them on demand.
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+
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+Required properties :
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+- compatible : shall contain only one of the following. The generic
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+ compatible "qcom,rpmcc" should be also included.
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+
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+ "qcom,rpmcc-msm8916", "qcom,rpmcc"
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+
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+- #clock-cells : shall contain 1
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+
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+Example:
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+ smd {
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+ compatible = "qcom,smd";
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+
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+ rpm {
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+ interrupts = <0 168 1>;
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+ qcom,ipc = <&apcs 8 0>;
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+ qcom,smd-edge = <15>;
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+
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+ rpm_requests {
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+ compatible = "qcom,rpm-msm8916";
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+ qcom,smd-channels = "rpm_requests";
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+
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+ rpmcc: clock-controller {
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+ compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
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+ #clock-cells = <1>;
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+ };
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+ };
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+ };
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+ };
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--- a/drivers/clk/qcom/Kconfig
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+++ b/drivers/clk/qcom/Kconfig
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@@ -2,6 +2,9 @@ config QCOM_GDSC
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bool
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select PM_GENERIC_DOMAINS if PM
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+config QCOM_RPMCC
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+ bool
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+
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config COMMON_CLK_QCOM
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tristate "Support for Qualcomm's clock controllers"
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depends on OF
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@@ -9,6 +12,19 @@ config COMMON_CLK_QCOM
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select REGMAP_MMIO
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select RESET_CONTROLLER
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+config QCOM_CLK_SMD_RPM
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+ tristate "RPM over SMD based Clock Controller"
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+ depends on COMMON_CLK_QCOM && QCOM_SMD_RPM
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+ select QCOM_RPMCC
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+ help
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+ The RPM (Resource Power Manager) is a dedicated hardware engine for
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+ managing the shared SoC resources in order to keep the lowest power
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+ profile. It communicates with other hardware subsystems via shared
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+ memory and accepts clock requests, aggregates the requests and turns
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+ the clocks on/off or scales them on demand.
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+ Say Y if you want to support the clocks exposed by the RPM on
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+ platforms such as apq8016, apq8084, msm8974 etc.
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+
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config APQ_GCC_8084
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tristate "APQ8084 Global Clock Controller"
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select QCOM_GDSC
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--- a/drivers/clk/qcom/Makefile
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+++ b/drivers/clk/qcom/Makefile
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@@ -28,3 +28,4 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8
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obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
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obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
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obj-$(CONFIG_KRAITCC) += krait-cc.o
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+obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
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--- /dev/null
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+++ b/drivers/clk/qcom/clk-smd-rpm.c
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@@ -0,0 +1,571 @@
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+/*
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+ * Copyright (c) 2016, Linaro Limited
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+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
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+ *
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+ * This software is licensed under the terms of the GNU General Public
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+ * License version 2, as published by the Free Software Foundation, and
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+ * may be copied, distributed, and modified under those terms.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/clk-provider.h>
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+#include <linux/err.h>
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+#include <linux/export.h>
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+#include <linux/init.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/mutex.h>
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+#include <linux/of.h>
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+#include <linux/of_device.h>
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+#include <linux/platform_device.h>
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+#include <linux/soc/qcom/smd-rpm.h>
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+
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+#include <dt-bindings/clock/qcom,rpmcc.h>
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+#include <dt-bindings/mfd/qcom-rpm.h>
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+
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+#define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773
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+#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370
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+#define QCOM_RPM_SMD_KEY_RATE 0x007a484b
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+#define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45
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+#define QCOM_RPM_SMD_KEY_STATE 0x54415453
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+#define QCOM_RPM_SCALING_ENABLE_ID 0x2
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+
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+#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id, \
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+ key) \
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+ static struct clk_smd_rpm _platform##_##_active; \
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+ static struct clk_smd_rpm _platform##_##_name = { \
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+ .rpm_res_type = (type), \
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+ .rpm_clk_id = (r_id), \
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+ .rpm_status_id = (stat_id), \
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+ .rpm_key = (key), \
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+ .peer = &_platform##_##_active, \
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+ .rate = INT_MAX, \
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+ .hw.init = &(struct clk_init_data){ \
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+ .ops = &clk_smd_rpm_ops, \
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+ .name = #_name, \
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+ .parent_names = (const char *[]){ "xo_board" }, \
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+ .num_parents = 1, \
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+ }, \
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+ }; \
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+ static struct clk_smd_rpm _platform##_##_active = { \
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+ .rpm_res_type = (type), \
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+ .rpm_clk_id = (r_id), \
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+ .rpm_status_id = (stat_id), \
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+ .active_only = true, \
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+ .rpm_key = (key), \
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+ .peer = &_platform##_##_name, \
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+ .rate = INT_MAX, \
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+ .hw.init = &(struct clk_init_data){ \
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+ .ops = &clk_smd_rpm_ops, \
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+ .name = #_active, \
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+ .parent_names = (const char *[]){ "xo_board" }, \
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+ .num_parents = 1, \
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+ }, \
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+ }
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+
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+#define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \
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+ stat_id, r, key) \
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+ static struct clk_smd_rpm _platform##_##_active; \
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+ static struct clk_smd_rpm _platform##_##_name = { \
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+ .rpm_res_type = (type), \
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+ .rpm_clk_id = (r_id), \
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+ .rpm_status_id = (stat_id), \
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+ .rpm_key = (key), \
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+ .branch = true, \
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+ .peer = &_platform##_##_active, \
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+ .rate = (r), \
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+ .hw.init = &(struct clk_init_data){ \
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+ .ops = &clk_smd_rpm_branch_ops, \
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+ .name = #_name, \
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+ .parent_names = (const char *[]){ "xo_board" }, \
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+ .num_parents = 1, \
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+ }, \
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+ }; \
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+ static struct clk_smd_rpm _platform##_##_active = { \
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+ .rpm_res_type = (type), \
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+ .rpm_clk_id = (r_id), \
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+ .rpm_status_id = (stat_id), \
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+ .active_only = true, \
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+ .rpm_key = (key), \
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+ .branch = true, \
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+ .peer = &_platform##_##_name, \
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+ .rate = (r), \
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+ .hw.init = &(struct clk_init_data){ \
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+ .ops = &clk_smd_rpm_branch_ops, \
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+ .name = #_active, \
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+ .parent_names = (const char *[]){ "xo_board" }, \
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+ .num_parents = 1, \
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+ }, \
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+ }
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+
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+#define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id) \
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+ __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \
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+ 0, QCOM_RPM_SMD_KEY_RATE)
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+
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+#define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r) \
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+ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, \
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+ r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE)
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+
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+#define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id) \
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+ __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \
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+ 0, QCOM_RPM_SMD_KEY_STATE)
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+
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+#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id) \
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+ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \
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+ QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
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+ QCOM_RPM_KEY_SOFTWARE_ENABLE)
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+
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+#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, r_id) \
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+ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \
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+ QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
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+ QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
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+
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+#define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
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+
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+struct clk_smd_rpm {
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+ const int rpm_res_type;
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+ const int rpm_key;
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+ const int rpm_clk_id;
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+ const int rpm_status_id;
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+ const bool active_only;
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+ bool enabled;
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+ bool branch;
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+ struct clk_smd_rpm *peer;
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+ struct clk_hw hw;
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+ unsigned long rate;
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+ struct qcom_smd_rpm *rpm;
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+};
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+
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+struct clk_smd_rpm_req {
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+ __le32 key;
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+ __le32 nbytes;
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+ __le32 value;
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+};
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+
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+struct rpm_cc {
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+ struct qcom_rpm *rpm;
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+ struct clk_hw_onecell_data data;
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+ struct clk_hw *hws[];
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+};
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+
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+struct rpm_smd_clk_desc {
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+ struct clk_smd_rpm **clks;
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+ size_t num_clks;
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+};
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+
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+static DEFINE_MUTEX(rpm_smd_clk_lock);
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+
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+static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)
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+{
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+ int ret;
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+ struct clk_smd_rpm_req req = {
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+ .key = cpu_to_le32(r->rpm_key),
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+ .nbytes = cpu_to_le32(sizeof(u32)),
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+ .value = cpu_to_le32(INT_MAX),
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+ };
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+
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+ ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
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+ r->rpm_res_type, r->rpm_clk_id, &req,
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+ sizeof(req));
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+ if (ret)
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+ return ret;
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+ ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
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+ r->rpm_res_type, r->rpm_clk_id, &req,
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+ sizeof(req));
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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+
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+static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
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+ unsigned long rate)
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+{
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+ struct clk_smd_rpm_req req = {
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+ .key = cpu_to_le32(r->rpm_key),
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+ .nbytes = cpu_to_le32(sizeof(u32)),
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+ .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
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+ };
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+
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+ return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
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+ r->rpm_res_type, r->rpm_clk_id, &req,
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+ sizeof(req));
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+}
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+
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+static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
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+ unsigned long rate)
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+{
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+ struct clk_smd_rpm_req req = {
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+ .key = cpu_to_le32(r->rpm_key),
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+ .nbytes = cpu_to_le32(sizeof(u32)),
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+ .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
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+ };
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+
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+ return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
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+ r->rpm_res_type, r->rpm_clk_id, &req,
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+ sizeof(req));
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+}
|
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+
|
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+static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
|
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+ unsigned long *active, unsigned long *sleep)
|
|
+{
|
|
+ *active = rate;
|
|
+
|
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+ /*
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+ * Active-only clocks don't care what the rate is during sleep. So,
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+ * they vote for zero.
|
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+ */
|
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+ if (r->active_only)
|
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+ *sleep = 0;
|
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+ else
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+ *sleep = *active;
|
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+}
|
|
+
|
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+static int clk_smd_rpm_prepare(struct clk_hw *hw)
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+{
|
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+ struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
|
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+ struct clk_smd_rpm *peer = r->peer;
|
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+ unsigned long this_rate = 0, this_sleep_rate = 0;
|
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+ unsigned long peer_rate = 0, peer_sleep_rate = 0;
|
|
+ unsigned long active_rate, sleep_rate;
|
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+ int ret = 0;
|
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+
|
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+ mutex_lock(&rpm_smd_clk_lock);
|
|
+
|
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+ /* Don't send requests to the RPM if the rate has not been set. */
|
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+ if (!r->rate)
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+ goto out;
|
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+
|
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+ to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
|
|
+
|
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+ /* Take peer clock's rate into account only if it's enabled. */
|
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+ if (peer->enabled)
|
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+ to_active_sleep(peer, peer->rate,
|
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+ &peer_rate, &peer_sleep_rate);
|
|
+
|
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+ active_rate = max(this_rate, peer_rate);
|
|
+
|
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+ if (r->branch)
|
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+ active_rate = !!active_rate;
|
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+
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+ ret = clk_smd_rpm_set_rate_active(r, active_rate);
|
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+ if (ret)
|
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+ goto out;
|
|
+
|
|
+ sleep_rate = max(this_sleep_rate, peer_sleep_rate);
|
|
+ if (r->branch)
|
|
+ sleep_rate = !!sleep_rate;
|
|
+
|
|
+ ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
|
|
+ if (ret)
|
|
+ /* Undo the active set vote and restore it */
|
|
+ ret = clk_smd_rpm_set_rate_active(r, peer_rate);
|
|
+
|
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+out:
|
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+ if (!ret)
|
|
+ r->enabled = true;
|
|
+
|
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+ mutex_unlock(&rpm_smd_clk_lock);
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static void clk_smd_rpm_unprepare(struct clk_hw *hw)
|
|
+{
|
|
+ struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
|
|
+ struct clk_smd_rpm *peer = r->peer;
|
|
+ unsigned long peer_rate = 0, peer_sleep_rate = 0;
|
|
+ unsigned long active_rate, sleep_rate;
|
|
+ int ret;
|
|
+
|
|
+ mutex_lock(&rpm_smd_clk_lock);
|
|
+
|
|
+ if (!r->rate)
|
|
+ goto out;
|
|
+
|
|
+ /* Take peer clock's rate into account only if it's enabled. */
|
|
+ if (peer->enabled)
|
|
+ to_active_sleep(peer, peer->rate, &peer_rate,
|
|
+ &peer_sleep_rate);
|
|
+
|
|
+ active_rate = r->branch ? !!peer_rate : peer_rate;
|
|
+ ret = clk_smd_rpm_set_rate_active(r, active_rate);
|
|
+ if (ret)
|
|
+ goto out;
|
|
+
|
|
+ sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
|
|
+ ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
|
|
+ if (ret)
|
|
+ goto out;
|
|
+
|
|
+ r->enabled = false;
|
|
+
|
|
+out:
|
|
+ mutex_unlock(&rpm_smd_clk_lock);
|
|
+}
|
|
+
|
|
+static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
+ unsigned long parent_rate)
|
|
+{
|
|
+ struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
|
|
+ struct clk_smd_rpm *peer = r->peer;
|
|
+ unsigned long active_rate, sleep_rate;
|
|
+ unsigned long this_rate = 0, this_sleep_rate = 0;
|
|
+ unsigned long peer_rate = 0, peer_sleep_rate = 0;
|
|
+ int ret = 0;
|
|
+
|
|
+ mutex_lock(&rpm_smd_clk_lock);
|
|
+
|
|
+ if (!r->enabled)
|
|
+ goto out;
|
|
+
|
|
+ to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
|
|
+
|
|
+ /* Take peer clock's rate into account only if it's enabled. */
|
|
+ if (peer->enabled)
|
|
+ to_active_sleep(peer, peer->rate,
|
|
+ &peer_rate, &peer_sleep_rate);
|
|
+
|
|
+ active_rate = max(this_rate, peer_rate);
|
|
+ ret = clk_smd_rpm_set_rate_active(r, active_rate);
|
|
+ if (ret)
|
|
+ goto out;
|
|
+
|
|
+ sleep_rate = max(this_sleep_rate, peer_sleep_rate);
|
|
+ ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
|
|
+ if (ret)
|
|
+ goto out;
|
|
+
|
|
+ r->rate = rate;
|
|
+
|
|
+out:
|
|
+ mutex_unlock(&rpm_smd_clk_lock);
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
+ unsigned long *parent_rate)
|
|
+{
|
|
+ /*
|
|
+ * RPM handles rate rounding and we don't have a way to
|
|
+ * know what the rate will be, so just return whatever
|
|
+ * rate is requested.
|
|
+ */
|
|
+ return rate;
|
|
+}
|
|
+
|
|
+static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
|
|
+ unsigned long parent_rate)
|
|
+{
|
|
+ struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
|
|
+
|
|
+ /*
|
|
+ * RPM handles rate rounding and we don't have a way to
|
|
+ * know what the rate will be, so just return whatever
|
|
+ * rate was set.
|
|
+ */
|
|
+ return r->rate;
|
|
+}
|
|
+
|
|
+static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
|
|
+{
|
|
+ int ret;
|
|
+ struct clk_smd_rpm_req req = {
|
|
+ .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
|
|
+ .nbytes = cpu_to_le32(sizeof(u32)),
|
|
+ .value = cpu_to_le32(1),
|
|
+ };
|
|
+
|
|
+ ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
|
|
+ QCOM_SMD_RPM_MISC_CLK,
|
|
+ QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
|
|
+ if (ret) {
|
|
+ pr_err("RPM clock scaling (sleep set) not enabled!\n");
|
|
+ return ret;
|
|
+ }
|
|
+
|
|
+ ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
|
|
+ QCOM_SMD_RPM_MISC_CLK,
|
|
+ QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
|
|
+ if (ret) {
|
|
+ pr_err("RPM clock scaling (active set) not enabled!\n");
|
|
+ return ret;
|
|
+ }
|
|
+
|
|
+ pr_debug("%s: RPM clock scaling is enabled\n", __func__);
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct clk_ops clk_smd_rpm_ops = {
|
|
+ .prepare = clk_smd_rpm_prepare,
|
|
+ .unprepare = clk_smd_rpm_unprepare,
|
|
+ .set_rate = clk_smd_rpm_set_rate,
|
|
+ .round_rate = clk_smd_rpm_round_rate,
|
|
+ .recalc_rate = clk_smd_rpm_recalc_rate,
|
|
+};
|
|
+
|
|
+static const struct clk_ops clk_smd_rpm_branch_ops = {
|
|
+ .prepare = clk_smd_rpm_prepare,
|
|
+ .unprepare = clk_smd_rpm_unprepare,
|
|
+ .round_rate = clk_smd_rpm_round_rate,
|
|
+ .recalc_rate = clk_smd_rpm_recalc_rate,
|
|
+};
|
|
+
|
|
+/* msm8916 */
|
|
+DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
|
|
+DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
|
|
+DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
|
|
+DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
|
|
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1);
|
|
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2);
|
|
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4);
|
|
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5);
|
|
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1);
|
|
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2);
|
|
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4);
|
|
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5);
|
|
+
|
|
+static struct clk_smd_rpm *msm8916_clks[] = {
|
|
+ [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
|
|
+ [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
|
|
+ [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
|
|
+ [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
|
|
+ [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
|
|
+ [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
|
|
+ [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
|
|
+ [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
|
|
+ [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
|
|
+ [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
|
|
+ [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
|
|
+ [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
|
|
+ [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
|
|
+ [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
|
|
+ [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
|
|
+ [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
|
|
+ [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
|
|
+ [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
|
|
+ [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
|
|
+ [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
|
|
+ [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
|
|
+ [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
|
|
+ [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
|
|
+ [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
|
|
+};
|
|
+
|
|
+static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
|
|
+ .clks = msm8916_clks,
|
|
+ .num_clks = ARRAY_SIZE(msm8916_clks),
|
|
+};
|
|
+
|
|
+static const struct of_device_id rpm_smd_clk_match_table[] = {
|
|
+ { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
|
|
+ { }
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
|
|
+
|
|
+static int rpm_smd_clk_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct clk_hw **hws;
|
|
+ struct rpm_cc *rcc;
|
|
+ struct clk_hw_onecell_data *data;
|
|
+ int ret;
|
|
+ size_t num_clks, i;
|
|
+ struct qcom_smd_rpm *rpm;
|
|
+ struct clk_smd_rpm **rpm_smd_clks;
|
|
+ const struct rpm_smd_clk_desc *desc;
|
|
+
|
|
+ rpm = dev_get_drvdata(pdev->dev.parent);
|
|
+ if (!rpm) {
|
|
+ dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
|
|
+ return -ENODEV;
|
|
+ }
|
|
+
|
|
+ desc = of_device_get_match_data(&pdev->dev);
|
|
+ if (!desc)
|
|
+ return -EINVAL;
|
|
+
|
|
+ rpm_smd_clks = desc->clks;
|
|
+ num_clks = desc->num_clks;
|
|
+
|
|
+ rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*hws) * num_clks,
|
|
+ GFP_KERNEL);
|
|
+ if (!rcc)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ hws = rcc->hws;
|
|
+ data = &rcc->data;
|
|
+ data->num = num_clks;
|
|
+
|
|
+ for (i = 0; i < num_clks; i++) {
|
|
+ if (!rpm_smd_clks[i]) {
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ rpm_smd_clks[i]->rpm = rpm;
|
|
+
|
|
+ ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
|
|
+ if (ret)
|
|
+ goto err;
|
|
+ }
|
|
+
|
|
+ ret = clk_smd_rpm_enable_scaling(rpm);
|
|
+ if (ret)
|
|
+ goto err;
|
|
+
|
|
+ for (i = 0; i < num_clks; i++) {
|
|
+ if (!rpm_smd_clks[i]) {
|
|
+ data->hws[i] = ERR_PTR(-ENOENT);
|
|
+ continue;
|
|
+ }
|
|
+
|
|
+ ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
|
|
+ if (ret)
|
|
+ goto err;
|
|
+ }
|
|
+
|
|
+ ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
|
|
+ data);
|
|
+ if (ret)
|
|
+ goto err;
|
|
+
|
|
+ return 0;
|
|
+err:
|
|
+ dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static int rpm_smd_clk_remove(struct platform_device *pdev)
|
|
+{
|
|
+ of_clk_del_provider(pdev->dev.of_node);
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct platform_driver rpm_smd_clk_driver = {
|
|
+ .driver = {
|
|
+ .name = "qcom-clk-smd-rpm",
|
|
+ .of_match_table = rpm_smd_clk_match_table,
|
|
+ },
|
|
+ .probe = rpm_smd_clk_probe,
|
|
+ .remove = rpm_smd_clk_remove,
|
|
+};
|
|
+
|
|
+static int __init rpm_smd_clk_init(void)
|
|
+{
|
|
+ return platform_driver_register(&rpm_smd_clk_driver);
|
|
+}
|
|
+core_initcall(rpm_smd_clk_init);
|
|
+
|
|
+static void __exit rpm_smd_clk_exit(void)
|
|
+{
|
|
+ platform_driver_unregister(&rpm_smd_clk_driver);
|
|
+}
|
|
+module_exit(rpm_smd_clk_exit);
|
|
+
|
|
+MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
|
|
+MODULE_LICENSE("GPL v2");
|
|
+MODULE_ALIAS("platform:qcom-clk-smd-rpm");
|
|
--- /dev/null
|
|
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
|
|
@@ -0,0 +1,45 @@
|
|
+/*
|
|
+ * Copyright 2015 Linaro Limited
|
|
+ *
|
|
+ * This software is licensed under the terms of the GNU General Public
|
|
+ * License version 2, as published by the Free Software Foundation, and
|
|
+ * may be copied, distributed, and modified under those terms.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ */
|
|
+
|
|
+#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
|
|
+#define _DT_BINDINGS_CLK_MSM_RPMCC_H
|
|
+
|
|
+/* msm8916 */
|
|
+#define RPM_SMD_XO_CLK_SRC 0
|
|
+#define RPM_SMD_XO_A_CLK_SRC 1
|
|
+#define RPM_SMD_PCNOC_CLK 2
|
|
+#define RPM_SMD_PCNOC_A_CLK 3
|
|
+#define RPM_SMD_SNOC_CLK 4
|
|
+#define RPM_SMD_SNOC_A_CLK 5
|
|
+#define RPM_SMD_BIMC_CLK 6
|
|
+#define RPM_SMD_BIMC_A_CLK 7
|
|
+#define RPM_SMD_QDSS_CLK 8
|
|
+#define RPM_SMD_QDSS_A_CLK 9
|
|
+#define RPM_SMD_BB_CLK1 10
|
|
+#define RPM_SMD_BB_CLK1_A 11
|
|
+#define RPM_SMD_BB_CLK2 12
|
|
+#define RPM_SMD_BB_CLK2_A 13
|
|
+#define RPM_SMD_RF_CLK1 14
|
|
+#define RPM_SMD_RF_CLK1_A 15
|
|
+#define RPM_SMD_RF_CLK2 16
|
|
+#define RPM_SMD_RF_CLK2_A 17
|
|
+#define RPM_SMD_BB_CLK1_PIN 18
|
|
+#define RPM_SMD_BB_CLK1_A_PIN 19
|
|
+#define RPM_SMD_BB_CLK2_PIN 20
|
|
+#define RPM_SMD_BB_CLK2_A_PIN 21
|
|
+#define RPM_SMD_RF_CLK1_PIN 22
|
|
+#define RPM_SMD_RF_CLK1_A_PIN 23
|
|
+#define RPM_SMD_RF_CLK2_PIN 24
|
|
+#define RPM_SMD_RF_CLK2_A_PIN 25
|
|
+
|
|
+#endif
|