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Changelog: * https://www.kernel.org/pub/linux/kernel/v4.x/ChangeLog-4.1.5 Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 46598
103 lines
3.1 KiB
Diff
103 lines
3.1 KiB
Diff
From 7fbbca069587b7f467e76f583ad640977de1a4ff Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Fri, 18 Jul 2014 15:28:02 -0300
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Subject: [PATCH] clk: sunxi: mod1 clock support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The module 1 type of clocks consist of a gate and a mux and are used on
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the audio blocks to mux and gate the PLL2 outputs for AC97, IIS or
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SPDIF. This commit adds support for them on the sunxi clock driver.
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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drivers/clk/sunxi/Makefile | 1 +
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drivers/clk/sunxi/clk-a10-mod1.c | 69 ++++++++++++++++++++++++++++++++++++++++
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2 files changed, 70 insertions(+)
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create mode 100644 drivers/clk/sunxi/clk-a10-mod1.c
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--- a/drivers/clk/sunxi/Makefile
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+++ b/drivers/clk/sunxi/Makefile
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@@ -5,6 +5,7 @@
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obj-y += clk-sunxi.o clk-factors.o
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obj-y += clk-a10-codec.o
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obj-y += clk-a10-hosc.o
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+obj-y += clk-a10-mod1.o
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obj-y += clk-a10-pll2.o
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obj-y += clk-a20-gmac.o
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obj-y += clk-mod0.o
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--- /dev/null
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+++ b/drivers/clk/sunxi/clk-a10-mod1.c
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@@ -0,0 +1,69 @@
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+/*
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+ * Copyright 2013 Emilio López
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+ *
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+ * Emilio López <emilio@elopez.com.ar>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/clk-provider.h>
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+#include <linux/clkdev.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+
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+static DEFINE_SPINLOCK(mod1_lock);
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+
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+#define SUN4I_MOD1_ENABLE 31
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+#define SUN4I_MOD1_MUX 16
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+#define SUN4I_MOD1_MUX_WIDTH 2
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+#define SUN4I_MOD1_MAX_PARENTS 4
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+
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+static void __init sun4i_mod1_clk_setup(struct device_node *node)
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+{
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+ struct clk *clk;
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+ struct clk_mux *mux;
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+ struct clk_gate *gate;
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+ const char *parents[4];
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+ const char *clk_name = node->name;
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+ void __iomem *reg;
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+ int i = 0;
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+
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+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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+ if (!mux || !gate) {
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+ kfree(mux);
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+ kfree(gate);
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+ return;
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+ }
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+
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+ of_property_read_string(node, "clock-output-names", &clk_name);
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+ reg = of_iomap(node, 0);
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+
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+ while (i < SUN4I_MOD1_MAX_PARENTS &&
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+ (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
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+ i++;
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+
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+ gate->reg = reg;
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+ gate->bit_idx = SUN4I_MOD1_ENABLE;
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+ gate->lock = &mod1_lock;
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+ mux->reg = reg;
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+ mux->shift = SUN4I_MOD1_MUX;
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+ mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1;
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+ mux->lock = &mod1_lock;
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+
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+ clk = clk_register_composite(NULL, clk_name, parents, i,
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+ &mux->hw, &clk_mux_ops,
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+ NULL, NULL,
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+ &gate->hw, &clk_gate_ops, 0);
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+ if (!IS_ERR(clk))
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+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
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+}
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+CLK_OF_DECLARE(sun4i_mod1, "allwinner,sun4i-a10-mod1-clk", sun4i_mod1_clk_setup);
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