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ff08b09570
All (still relevant) patches were refresh. The following patches were dropped because they are applied upstream: - 0003-MIPS-lantiq-handle-vmmc-memory-reservation.patch - 0005-MIPS-lantiq-add-reset-controller-api-support.patch - 0006-MIPS-lantiq-reboot-gphy-on-restart.patch - 0009-MIPS-lantiq-command-line-work-around.patch - 0010-MIPS-lantiq-export-soc-type.patch - 0011-lantiq-add-support-for-xrx200-firmware-depending-on-.patch - 0037-MIPS-lantiq-move-eiu-init-after-irq_domain-register.patch Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> SVN-Revision: 46216
126 lines
3.9 KiB
Diff
126 lines
3.9 KiB
Diff
From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 9 Sep 2014 23:12:15 +0200
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Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/mtd/nand/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 63 insertions(+)
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--- a/drivers/mtd/nand/xway_nand.c
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+++ b/drivers/mtd/nand/xway_nand.c
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@@ -54,8 +54,27 @@
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#define NAND_CON_CSMUX (1 << 1)
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#define NAND_CON_NANDM 1
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+#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr))
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+#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400)
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+#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080)
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+
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static u32 xway_latchcmd;
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+/*
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+ * req_mask provides a mechanism to prevent interference between
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+ * nand and pci (probably only relevant for the BT Home Hub 2B).
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+ * Setting it causes the corresponding pci req pins to be masked
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+ * during nand access, and also moves ebu locking from the read/write
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+ * functions to the chip select function to ensure that the whole
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+ * operation runs with interrupts disabled.
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+ * In addition it switches on some extra waiting in xway_cmd_ctrl().
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+ * This seems to be necessary if the ebu_cs1 pin has open-drain disabled,
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+ * which in turn seems to be necessary for the nor chip to be recognised
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+ * reliably, on a board (Home Hub 2B again) which has both nor and nand.
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+ */
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+
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+static __be32 req_mask = 0;
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+
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static void xway_reset_chip(struct nand_chip *chip)
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{
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unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
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@@ -86,12 +105,24 @@ static void xway_select_chip(struct mtd_
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case -1:
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ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
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ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
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+
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+ if (req_mask) {
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+ /* Unmask all external PCI request */
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+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16);
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+ }
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spin_unlock_irqrestore(&ebu_lock, csflags);
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+
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break;
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case 0:
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spin_lock_irqsave(&ebu_lock, csflags);
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+ if (req_mask) {
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+ /* Mask all external PCI request */
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+ DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16);
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+ }
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+
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ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
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ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
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+
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break;
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default:
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BUG();
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@@ -103,6 +134,12 @@ static void xway_cmd_ctrl(struct mtd_inf
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struct nand_chip *this = mtd->priv;
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unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
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+ if (req_mask) {
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+ if (cmd != NAND_CMD_STATUS)
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+ ltq_ebu_w32(EBU_NAND_WAIT, 0); /* Clear nand ready */
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+ }
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+
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+
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_CLE)
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xway_latchcmd = NAND_WRITE_CMD;
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@@ -115,6 +152,24 @@ static void xway_cmd_ctrl(struct mtd_inf
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while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
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;
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}
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+
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+ if (req_mask) {
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+ /*
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+ * program and erase have their own busy handlers
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+ * status and sequential in needs no delay
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+ */
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+ switch (cmd) {
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+ case NAND_CMD_ERASE1:
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+ case NAND_CMD_SEQIN:
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+ case NAND_CMD_STATUS:
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+ case NAND_CMD_READID:
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+ return;
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+ }
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+
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+ /* wait until command is processed */
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+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
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+ ;
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+ }
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}
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static int xway_dev_ready(struct mtd_info *mtd)
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@@ -157,6 +212,8 @@ static int xway_nand_probe(struct platfo
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{
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struct nand_chip *this = platform_get_drvdata(pdev);
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unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
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+ const __be32 *req_mask_ptr = of_get_property(pdev->dev.of_node,
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+ "req-mask", NULL);
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const __be32 *cs = of_get_property(pdev->dev.of_node,
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"lantiq,cs", NULL);
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u32 cs_flag = 0;
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@@ -165,6 +222,12 @@ static int xway_nand_probe(struct platfo
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if (cs && (*cs == 1))
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cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
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+ /*
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+ * Load the PCI req lines to mask from the device tree. If the
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+ * property is not present, setting req_mask to 0 disables masking.
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+ */
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+ req_mask = (req_mask_ptr ? *req_mask_ptr : 0);
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+
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/* setup the EBU to run in NAND mode on our base addr */
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ltq_ebu_w32(CPHYSADDR(nandaddr)
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| ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);
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