mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2024-12-16 20:04:36 +00:00
109 lines
3.1 KiB
Diff
109 lines
3.1 KiB
Diff
--- a/arch/powerpc/boot/dts/canyonlands.dts
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+++ b/arch/powerpc/boot/dts/canyonlands.dts
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@@ -40,6 +40,7 @@
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d-cache-size = <32768>;
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dcr-controller;
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dcr-access-method = "native";
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+ next-level-cache = <&L2C0>;
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};
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};
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@@ -104,6 +105,16 @@
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dcr-reg = <0x00c 0x002>;
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};
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+ L2C0: l2c {
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+ compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
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+ dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
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+ 0x030 0x008>; /* L2 cache DCR's */
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+ cache-line-size = <32>; /* 32 bytes */
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+ cache-size = <262144>; /* L2, 256K */
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+ interrupt-parent = <&UIC1>;
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+ interrupts = <11 1>;
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+ };
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+
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plb {
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compatible = "ibm,plb-460ex", "ibm,plb4";
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#address-cells = <2>;
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@@ -131,6 +142,43 @@
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/*RXDE*/ 0x5 0x4>;
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};
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+ USB0: ehci@bffd0400 {
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+ compatible = "ibm,usb-ehci-460ex", "usb-ehci";
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+ interrupt-parent = <&UIC2>;
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+ interrupts = <0x1d 4>;
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+ reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
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+ };
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+
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+ USB1: usb@bffd0000 {
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+ compatible = "ohci-le";
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+ reg = <4 0xbffd0000 0x60>;
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+ interrupt-parent = <&UIC2>;
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+ interrupts = <0x1e 4>;
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+ };
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+
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+ USBOTG0: usbotg@bff80000 {
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+ compatible = "amcc,usb-otg-460ex";
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+ reg = <4 0xbff80000 0x10000>;
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+ interrupt-parent = <&USBOTG0>;
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+ interrupts = <0 1 2>;
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+ #interrupt-cells = <1>;
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+ #address-cells = <0>;
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+ #size-cells = <0>;
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+ interrupt-map = </* USB-OTG */ 0 &UIC2 0x1c 4
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+ /* HIGH-POWER */ 1 &UIC1 0x1a 8
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+ /* DMA */ 2 &UIC0 0xc 4>;
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+ interrupt-map-mask = <0xffffffff>;
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+ };
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+
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+ SATA0: sata@bffd1000 {
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+ compatible = "amcc,sata-460ex";
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+ reg = <4 0xbffd1000 0x800 /* SATA */
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+ 4 0xbffd0800 0x400>; /* AHBDMA */
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+ interrupt-parent = <&UIC3>;
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+ interrupts = <0 4 /* SATA */
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+ 5 4>; /* AHBDMA */
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+ };
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+
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POB0: opb {
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compatible = "ibm,opb-460ex", "ibm,opb";
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#address-cells = <1>;
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@@ -222,6 +270,12 @@
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reg = <0xef600700 0x00000014>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x2 0x4>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ rtc@68 {
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+ compatible = "stm,m41t80";
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+ reg = <68>;
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+ };
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};
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IIC1: i2c@ef600800 {
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@@ -331,6 +385,7 @@
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* later cannot be changed
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*/
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ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
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+ 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
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0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
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/* Inbound 2GB range starting at 0 */
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@@ -361,6 +416,7 @@
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* later cannot be changed
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*/
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ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
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+ 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
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0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
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/* Inbound 2GB range starting at 0 */
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@@ -402,6 +458,7 @@
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* later cannot be changed
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*/
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ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
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+ 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
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0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
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/* Inbound 2GB range starting at 0 */
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