66 lines
2.4 KiB
Diff
66 lines
2.4 KiB
Diff
From: Johan Almbladh <johan.almbladh@anyfinetworks.com>
|
|
Date: Tue, 5 Oct 2021 18:54:02 +0200
|
|
Subject: [PATCH] MIPS: uasm: Enable muhu opcode for MIPS R6
|
|
|
|
Enable the 'muhu' instruction, complementing the existing 'mulu', needed
|
|
to implement a MIPS32 BPF JIT.
|
|
|
|
Also fix a typo in the existing definition of 'dmulu'.
|
|
|
|
Signed-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>
|
|
|
|
This patch is a dependency for my 32-bit MIPS eBPF JIT.
|
|
|
|
Signed-off-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
|
|
---
|
|
|
|
--- a/arch/mips/include/asm/uasm.h
|
|
+++ b/arch/mips/include/asm/uasm.h
|
|
@@ -145,6 +145,7 @@ Ip_u1(_mtlo);
|
|
Ip_u3u1u2(_mul);
|
|
Ip_u1u2(_multu);
|
|
Ip_u3u1u2(_mulu);
|
|
+Ip_u3u1u2(_muhu);
|
|
Ip_u3u1u2(_nor);
|
|
Ip_u3u1u2(_or);
|
|
Ip_u2u1u3(_ori);
|
|
--- a/arch/mips/mm/uasm-mips.c
|
|
+++ b/arch/mips/mm/uasm-mips.c
|
|
@@ -90,7 +90,7 @@ static const struct insn insn_table[insn
|
|
RS | RT | RD},
|
|
[insn_dmtc0] = {M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
|
|
[insn_dmultu] = {M(spec_op, 0, 0, 0, 0, dmultu_op), RS | RT},
|
|
- [insn_dmulu] = {M(spec_op, 0, 0, 0, dmult_dmul_op, dmultu_op),
|
|
+ [insn_dmulu] = {M(spec_op, 0, 0, 0, dmultu_dmulu_op, dmultu_op),
|
|
RS | RT | RD},
|
|
[insn_drotr] = {M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE},
|
|
[insn_drotr32] = {M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE},
|
|
@@ -150,6 +150,8 @@ static const struct insn insn_table[insn
|
|
[insn_mtlo] = {M(spec_op, 0, 0, 0, 0, mtlo_op), RS},
|
|
[insn_mulu] = {M(spec_op, 0, 0, 0, multu_mulu_op, multu_op),
|
|
RS | RT | RD},
|
|
+ [insn_muhu] = {M(spec_op, 0, 0, 0, multu_muhu_op, multu_op),
|
|
+ RS | RT | RD},
|
|
#ifndef CONFIG_CPU_MIPSR6
|
|
[insn_mul] = {M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
|
|
#else
|
|
--- a/arch/mips/mm/uasm.c
|
|
+++ b/arch/mips/mm/uasm.c
|
|
@@ -59,7 +59,7 @@ enum opcode {
|
|
insn_lddir, insn_ldpte, insn_ldx, insn_lh, insn_lhu, insn_ll, insn_lld,
|
|
insn_lui, insn_lw, insn_lwu, insn_lwx, insn_mfc0, insn_mfhc0, insn_mfhi,
|
|
insn_mflo, insn_modu, insn_movn, insn_movz, insn_mtc0, insn_mthc0,
|
|
- insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_nor,
|
|
+ insn_mthi, insn_mtlo, insn_mul, insn_multu, insn_mulu, insn_muhu, insn_nor,
|
|
insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sb, insn_sc,
|
|
insn_scd, insn_seleqz, insn_selnez, insn_sd, insn_sh, insn_sll,
|
|
insn_sllv, insn_slt, insn_slti, insn_sltiu, insn_sltu, insn_sra,
|
|
@@ -344,6 +344,7 @@ I_u1(_mtlo)
|
|
I_u3u1u2(_mul)
|
|
I_u1u2(_multu)
|
|
I_u3u1u2(_mulu)
|
|
+I_u3u1u2(_muhu)
|
|
I_u3u1u2(_nor)
|
|
I_u3u1u2(_or)
|
|
I_u2u1u3(_ori)
|