123 lines
4.2 KiB
Diff
123 lines
4.2 KiB
Diff
From 39d42ce5031d2a4f92fa203b87acfbab340b15a2 Mon Sep 17 00:00:00 2001
|
|
From: Stephen Boyd <sboyd@codeaurora.org>
|
|
Date: Fri, 20 Mar 2015 23:45:22 -0700
|
|
Subject: [PATCH 2/2] clk: Avoid sending high rates to downstream clocks during
|
|
set_rate
|
|
|
|
If a clock is on and we call clk_set_rate() on it we may get into
|
|
a situation where the clock temporarily increases in rate
|
|
dramatically while we walk the tree and call .set_rate() ops. For
|
|
example, consider a case where a PLL feeds into a divider.
|
|
Initially the divider is set to divide by 1 and the PLL is
|
|
running fairly slow (100MHz). The downstream consumer of the
|
|
divider output can only handle rates =< 400 MHz, but the divider
|
|
can only choose between divisors of 1 and 4.
|
|
|
|
+-----+ +----------------+
|
|
| PLL |-->| div 1 or div 4 |---> consumer device
|
|
+-----+ +----------------+
|
|
|
|
To achieve a rate of 400MHz on the output of the divider, we
|
|
would have to set the rate of the PLL to 1.6 GHz and then divide
|
|
it by 4. The current code would set the PLL to 1.6GHz first while
|
|
the divider is still set to 1, thus causing the downstream
|
|
consumer of the clock to receive a few clock cycles of 1.6GHz
|
|
clock (far beyond it's maximum acceptable rate). We should be
|
|
changing the divider first before increasing the PLL rate to
|
|
avoid this problem.
|
|
|
|
Therefore, set the rate of any child clocks that are increasing
|
|
in rate from their current rate so that they can increase their
|
|
dividers if necessary. We assume that there isn't such a thing as
|
|
minimum rate requirements.
|
|
|
|
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
|
|
Signed-off-by: Ram Chandra Jangir <rjangi@codeaurora.org>
|
|
---
|
|
drivers/clk/clk.c | 34 ++++++++++++++++++++++------------
|
|
1 file changed, 22 insertions(+), 12 deletions(-)
|
|
|
|
--- a/drivers/clk/clk.c
|
|
+++ b/drivers/clk/clk.c
|
|
@@ -1427,21 +1427,24 @@ static struct clk_core *clk_propagate_ra
|
|
* walk down a subtree and set the new rates notifying the rate
|
|
* change on the way
|
|
*/
|
|
-static void clk_change_rate(struct clk_core *core)
|
|
+static void
|
|
+clk_change_rate(struct clk_core *core, unsigned long best_parent_rate)
|
|
{
|
|
struct clk_core *child;
|
|
struct hlist_node *tmp;
|
|
unsigned long old_rate;
|
|
- unsigned long best_parent_rate = 0;
|
|
bool skip_set_rate = false;
|
|
struct clk_core *old_parent;
|
|
|
|
- old_rate = core->rate;
|
|
+ hlist_for_each_entry(child, &core->children, child_node) {
|
|
+ /* Skip children who will be reparented to another clock */
|
|
+ if (child->new_parent && child->new_parent != core)
|
|
+ continue;
|
|
+ if (child->new_rate > child->rate)
|
|
+ clk_change_rate(child, core->new_rate);
|
|
+ }
|
|
|
|
- if (core->new_parent)
|
|
- best_parent_rate = core->new_parent->rate;
|
|
- else if (core->parent)
|
|
- best_parent_rate = core->parent->rate;
|
|
+ old_rate = core->rate;
|
|
|
|
if (core->new_parent && core->new_parent != core->parent) {
|
|
old_parent = __clk_set_parent_before(core, core->new_parent);
|
|
@@ -1467,7 +1470,7 @@ static void clk_change_rate(struct clk_c
|
|
|
|
trace_clk_set_rate_complete(core, core->new_rate);
|
|
|
|
- core->rate = clk_recalc(core, best_parent_rate);
|
|
+ core->rate = core->new_rate;
|
|
|
|
if (core->notifier_count && old_rate != core->rate)
|
|
__clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate);
|
|
@@ -1483,12 +1486,13 @@ static void clk_change_rate(struct clk_c
|
|
/* Skip children who will be reparented to another clock */
|
|
if (child->new_parent && child->new_parent != core)
|
|
continue;
|
|
- clk_change_rate(child);
|
|
+ if (child->new_rate != child->rate)
|
|
+ clk_change_rate(child, core->new_rate);
|
|
}
|
|
|
|
/* handle the new child who might not be in core->children yet */
|
|
- if (core->new_child)
|
|
- clk_change_rate(core->new_child);
|
|
+ if (core->new_child && core->new_child->new_rate != core->new_child->rate)
|
|
+ clk_change_rate(core->new_child, core->new_rate);
|
|
}
|
|
|
|
static int clk_core_set_rate_nolock(struct clk_core *core,
|
|
@@ -1497,6 +1501,7 @@ static int clk_core_set_rate_nolock(stru
|
|
struct clk_core *top, *fail_clk;
|
|
unsigned long rate = req_rate;
|
|
int ret = 0;
|
|
+ unsigned long parent_rate;
|
|
|
|
if (!core)
|
|
return 0;
|
|
@@ -1522,8 +1527,13 @@ static int clk_core_set_rate_nolock(stru
|
|
return -EBUSY;
|
|
}
|
|
|
|
+ if (top->parent)
|
|
+ parent_rate = top->parent->rate;
|
|
+ else
|
|
+ parent_rate = 0;
|
|
+
|
|
/* change the rates */
|
|
- clk_change_rate(top);
|
|
+ clk_change_rate(top, parent_rate);
|
|
|
|
core->req_rate = req_rate;
|
|
|