458 lines
12 KiB
Diff
458 lines
12 KiB
Diff
From 0f31298eb0a9b2cd7990b709ff18229fadfa474b Mon Sep 17 00:00:00 2001
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From: Biwen Li <biwen.li@nxp.com>
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Date: Wed, 17 Apr 2019 18:58:38 +0800
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Subject: [PATCH] flextimer: support layerscape
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This is an integrated patch of flextimer for layerscape
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Signed-off-by: Biwen Li <biwen.li@nxp.com>
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Signed-off-by: Meng Yi <meng.yi@nxp.com>
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Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
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Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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---
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.../bindings/soc/fsl/layerscape/ftm-alarm.txt | 32 ++
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drivers/clocksource/fsl_ftm_timer.c | 8 +-
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drivers/soc/fsl/layerscape/ftm_alarm.c | 382 ++++++++++++++++++
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3 files changed, 418 insertions(+), 4 deletions(-)
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create mode 100644 Documentation/devicetree/bindings/soc/fsl/layerscape/ftm-alarm.txt
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create mode 100644 drivers/soc/fsl/layerscape/ftm_alarm.c
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/soc/fsl/layerscape/ftm-alarm.txt
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@@ -0,0 +1,32 @@
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+Freescale FlexTimer Module (FTM) Alarm
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+
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+Required properties:
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+
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+- compatible : Should be "fsl,ftm-alarm" or "fsl,<chip>-ftm-alarm", the
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+ supported chips include
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+ "fsl,ls1012a-ftm-alarm"
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+ "fsl,ls1021a-ftm-alarm"
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+ "fsl,ls1043a-ftm-alarm"
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+ "fsl,ls1046a-ftm-alarm"
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+ "fsl,ls1088a-ftm-alarm"
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+ "fsl,ls208xa-ftm-alarm"
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+- reg : Specifies base physical address and size of the register sets for the
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+ FlexTimer Module and base physical address of IP Powerdown Exception Control
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+ Register.
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+- reg-names: names of the mapped memory regions listed in regs property.
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+ should include the following entries:
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+ "ftm": Address of the register sets for FlexTimer Module
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+ "pmctrl": Address of IP Powerdown Exception Control register
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+- interrupts : Should be the FlexTimer Module interrupt.
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+- big-endian: If the host controller is big-endian mode, specify this property.
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+ The default endian mode is little-endian.
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+
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+Example:
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+ftm0: ftm0@29d0000 {
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+ compatible = "fsl,ls1043a-ftm-alarm";
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+ reg = <0x0 0x29d0000 0x0 0x10000>,
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+ <0x0 0x1ee2140 0x0 0x4>;
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+ reg-names = "ftm", "pmctrl";
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+ interrupts = <0 86 0x4>;
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+ big-endian;
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+};
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--- a/drivers/clocksource/fsl_ftm_timer.c
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+++ b/drivers/clocksource/fsl_ftm_timer.c
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@@ -83,11 +83,11 @@ static inline void ftm_counter_disable(v
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static inline void ftm_irq_acknowledge(void __iomem *base)
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{
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- u32 val;
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+ unsigned int timeout = 100;
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- val = ftm_readl(base + FTM_SC);
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- val &= ~FTM_SC_TOF;
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- ftm_writel(val, base + FTM_SC);
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+ while ((FTM_SC_TOF & ftm_readl(base + FTM_SC)) && timeout--)
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+ ftm_writel(ftm_readl(base + FTM_SC) & (~FTM_SC_TOF),
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+ base + FTM_SC);
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}
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static inline void ftm_irq_enable(void __iomem *base)
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--- /dev/null
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+++ b/drivers/soc/fsl/layerscape/ftm_alarm.c
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@@ -0,0 +1,382 @@
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+/*
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+ * Freescale FlexTimer Module (FTM) Alarm driver.
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+ *
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+ * Copyright 2014 Freescale Semiconductor, Inc.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * as published by the Free Software Foundation; either version 2
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+ * of the License, or (at your option) any later version.
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+ */
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+
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+#include <linux/device.h>
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+#include <linux/err.h>
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+#include <linux/interrupt.h>
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+#include <linux/io.h>
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+#include <linux/of_address.h>
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+#include <linux/of_irq.h>
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+#include <linux/platform_device.h>
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+#include <linux/of.h>
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+#include <linux/of_device.h>
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+#include <linux/libata.h>
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+#include <linux/module.h>
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+
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+#define FTM_SC 0x00
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+#define FTM_SC_CLK_SHIFT 3
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+#define FTM_SC_CLK_MASK (0x3 << FTM_SC_CLK_SHIFT)
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+#define FTM_SC_CLK(c) ((c) << FTM_SC_CLK_SHIFT)
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+#define FTM_SC_PS_MASK 0x7
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+#define FTM_SC_TOIE BIT(6)
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+#define FTM_SC_TOF BIT(7)
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+
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+#define FTM_SC_CLKS_FIXED_FREQ 0x02
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+
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+#define FTM_CNT 0x04
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+#define FTM_MOD 0x08
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+#define FTM_CNTIN 0x4C
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+
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+#define FIXED_FREQ_CLK 32000
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+#define MAX_FREQ_DIV (1 << FTM_SC_PS_MASK)
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+#define MAX_COUNT_VAL 0xffff
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+
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+static void __iomem *ftm1_base;
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+static void __iomem *rcpm_ftm_addr;
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+static void __iomem *scfg_scrachpad_addr;
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+static u32 alarm_freq;
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+static bool big_endian;
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+
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+enum pmu_endian_type {
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+ BIG_ENDIAN,
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+ LITTLE_ENDIAN,
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+};
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+
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+struct rcpm_cfg {
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+ enum pmu_endian_type big_endian; /* Big/Little endian of PMU module */
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+ u32 flextimer_set_bit; /* FTM is not powerdown during device LPM20 */
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+};
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+
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+static struct rcpm_cfg ls1012a_rcpm_cfg = {
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+ .big_endian = BIG_ENDIAN,
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+ .flextimer_set_bit = 0x20000,
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+};
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+
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+static struct rcpm_cfg ls1021a_rcpm_cfg = {
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+ .big_endian = BIG_ENDIAN,
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+ .flextimer_set_bit = 0x30000000,
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+};
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+
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+static struct rcpm_cfg ls1043a_rcpm_cfg = {
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+ .big_endian = BIG_ENDIAN,
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+ .flextimer_set_bit = 0x20000,
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+};
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+
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+static struct rcpm_cfg ls1046a_rcpm_cfg = {
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+ .big_endian = BIG_ENDIAN,
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+ .flextimer_set_bit = 0x20000,
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+};
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+
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+static struct rcpm_cfg ls1088a_rcpm_cfg = {
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+ .big_endian = LITTLE_ENDIAN,
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+ .flextimer_set_bit = 0x4000,
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+};
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+
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+static struct rcpm_cfg ls208xa_rcpm_cfg = {
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+ .big_endian = LITTLE_ENDIAN,
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+ .flextimer_set_bit = 0x4000,
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+};
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+
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+static struct rcpm_cfg lx2160a_rcpm_cfg = {
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+ .big_endian = LITTLE_ENDIAN,
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+ .flextimer_set_bit = 0x4000,
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+};
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+
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+static const struct of_device_id ippdexpcr_of_match[] = {
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+ { .compatible = "fsl,ls1012a-ftm-alarm", .data = &ls1012a_rcpm_cfg},
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+ { .compatible = "fsl,ls1021a-ftm-alarm", .data = &ls1021a_rcpm_cfg},
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+ { .compatible = "fsl,ls1043a-ftm-alarm", .data = &ls1043a_rcpm_cfg},
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+ { .compatible = "fsl,ls1046a-ftm-alarm", .data = &ls1046a_rcpm_cfg},
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+ { .compatible = "fsl,ls1088a-ftm-alarm", .data = &ls1088a_rcpm_cfg},
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+ { .compatible = "fsl,ls208xa-ftm-alarm", .data = &ls208xa_rcpm_cfg},
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+ { .compatible = "fsl,lx2160a-ftm-alarm", .data = &lx2160a_rcpm_cfg},
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, ippdexpcr_of_match);
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+
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+static inline u32 ftm_readl(void __iomem *addr)
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+{
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+ if (big_endian)
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+ return ioread32be(addr);
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+
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+ return ioread32(addr);
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+}
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+
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+static inline void ftm_writel(u32 val, void __iomem *addr)
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+{
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+ if (big_endian)
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+ iowrite32be(val, addr);
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+ else
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+ iowrite32(val, addr);
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+}
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+
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+static inline void ftm_counter_enable(void __iomem *base)
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+{
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+ u32 val;
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+
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+ /* select and enable counter clock source */
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+ val = ftm_readl(base + FTM_SC);
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+ val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
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+ val |= (FTM_SC_PS_MASK | FTM_SC_CLK(FTM_SC_CLKS_FIXED_FREQ));
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+ ftm_writel(val, base + FTM_SC);
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+}
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+
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+static inline void ftm_counter_disable(void __iomem *base)
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+{
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+ u32 val;
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+
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+ /* disable counter clock source */
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+ val = ftm_readl(base + FTM_SC);
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+ val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
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+ ftm_writel(val, base + FTM_SC);
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+}
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+
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+static inline void ftm_irq_acknowledge(void __iomem *base)
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+{
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+ unsigned int timeout = 100;
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+
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+ while ((FTM_SC_TOF & ftm_readl(base + FTM_SC)) && timeout--)
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+ ftm_writel(ftm_readl(base + FTM_SC) & (~FTM_SC_TOF),
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+ base + FTM_SC);
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+}
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+
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+static inline void ftm_irq_enable(void __iomem *base)
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+{
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+ u32 val;
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+
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+ val = ftm_readl(base + FTM_SC);
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+ val |= FTM_SC_TOIE;
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+ ftm_writel(val, base + FTM_SC);
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+}
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+
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+static inline void ftm_irq_disable(void __iomem *base)
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+{
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+ u32 val;
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+
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+ val = ftm_readl(base + FTM_SC);
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+ val &= ~FTM_SC_TOIE;
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+ ftm_writel(val, base + FTM_SC);
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+}
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+
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+static inline void ftm_reset_counter(void __iomem *base)
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+{
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+ /*
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+ * The CNT register contains the FTM counter value.
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+ * Reset clears the CNT register. Writing any value to COUNT
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+ * updates the counter with its initial value, CNTIN.
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+ */
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+ ftm_writel(0x00, base + FTM_CNT);
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+}
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+
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+static u32 time_to_cycle(unsigned long time)
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+{
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+ u32 cycle;
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+
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+ cycle = time * alarm_freq;
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+ if (cycle > MAX_COUNT_VAL) {
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+ pr_err("Out of alarm range.\n");
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+ cycle = 0;
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+ }
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+
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+ return cycle;
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+}
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+
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+static u32 cycle_to_time(u32 cycle)
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+{
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+ return cycle / alarm_freq + 1;
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+}
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+
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+static void ftm_clean_alarm(void)
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+{
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+ ftm_counter_disable(ftm1_base);
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+
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+ ftm_writel(0x00, ftm1_base + FTM_CNTIN);
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+ ftm_writel(~0U, ftm1_base + FTM_MOD);
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+
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+ ftm_reset_counter(ftm1_base);
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+}
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+
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+static int ftm_set_alarm(u64 cycle)
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+{
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+ ftm_irq_disable(ftm1_base);
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+
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+ /*
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+ * The counter increments until the value of MOD is reached,
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+ * at which point the counter is reloaded with the value of CNTIN.
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+ * The TOF (the overflow flag) bit is set when the FTM counter
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+ * changes from MOD to CNTIN. So we should using the cycle - 1.
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+ */
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+ ftm_writel(cycle - 1, ftm1_base + FTM_MOD);
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+
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+ ftm_counter_enable(ftm1_base);
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+
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+ ftm_irq_enable(ftm1_base);
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+
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+ return 0;
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+}
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+
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+static irqreturn_t ftm_alarm_interrupt(int irq, void *dev_id)
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+{
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+ ftm_irq_acknowledge(ftm1_base);
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+ ftm_irq_disable(ftm1_base);
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+ ftm_clean_alarm();
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static ssize_t ftm_alarm_show(struct device *dev,
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+ struct device_attribute *attr,
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+ char *buf)
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+{
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+ u32 count, val;
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+
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+ count = ftm_readl(ftm1_base + FTM_MOD);
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+ val = ftm_readl(ftm1_base + FTM_CNT);
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+ val = (count & MAX_COUNT_VAL) - val;
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+ val = cycle_to_time(val);
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+
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+ return sprintf(buf, "%u\n", val);
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+}
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+
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+static ssize_t ftm_alarm_store(struct device *dev,
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+ struct device_attribute *attr,
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+ const char *buf, size_t count)
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+{
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+ u32 cycle;
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+ unsigned long time;
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+
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+ if (kstrtoul(buf, 0, &time))
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+ return -EINVAL;
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+
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+ ftm_clean_alarm();
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+
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+ cycle = time_to_cycle(time);
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+ if (!cycle)
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+ return -EINVAL;
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+
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+ ftm_set_alarm(cycle);
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+
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+ return count;
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+}
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+
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+static struct device_attribute ftm_alarm_attributes = __ATTR(ftm_alarm, 0644,
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+ ftm_alarm_show, ftm_alarm_store);
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+
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+static int ftm_alarm_probe(struct platform_device *pdev)
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+{
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+ struct device_node *np = pdev->dev.of_node;
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+ struct resource *r;
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+ int irq;
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+ int ret;
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+ struct rcpm_cfg *rcpm_cfg;
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+ u32 ippdexpcr, flextimer;
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+ const struct of_device_id *of_id;
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+ enum pmu_endian_type endian;
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+
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+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ if (!r)
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+ return -ENODEV;
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+
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+ ftm1_base = devm_ioremap_resource(&pdev->dev, r);
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+ if (IS_ERR(ftm1_base))
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+ return PTR_ERR(ftm1_base);
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+
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+ of_id = of_match_node(ippdexpcr_of_match, np);
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+ if (!of_id)
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+ return -ENODEV;
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+
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+ rcpm_cfg = devm_kzalloc(&pdev->dev, sizeof(*rcpm_cfg), GFP_KERNEL);
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+ if (!rcpm_cfg)
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+ return -ENOMEM;
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+
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+ rcpm_cfg = (struct rcpm_cfg *)of_id->data;
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+ endian = rcpm_cfg->big_endian;
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+ flextimer = rcpm_cfg->flextimer_set_bit;
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+
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+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pmctrl");
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+ if (r) {
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+ rcpm_ftm_addr = devm_ioremap_resource(&pdev->dev, r);
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+ if (IS_ERR(rcpm_ftm_addr))
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+ return PTR_ERR(rcpm_ftm_addr);
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+ if (endian == BIG_ENDIAN)
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+ ippdexpcr = ioread32be(rcpm_ftm_addr);
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+ else
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+ ippdexpcr = ioread32(rcpm_ftm_addr);
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+ ippdexpcr |= flextimer;
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+ if (endian == BIG_ENDIAN)
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+ iowrite32be(ippdexpcr, rcpm_ftm_addr);
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+ else
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+ iowrite32(ippdexpcr, rcpm_ftm_addr);
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+
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+ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scrachpad");
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+ if (r) {
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+ scfg_scrachpad_addr = devm_ioremap_resource(&pdev->dev, r);
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+ iowrite32(ippdexpcr, scfg_scrachpad_addr);
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+ }
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+ }
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+
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+ irq = irq_of_parse_and_map(np, 0);
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+ if (irq <= 0) {
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+ pr_err("ftm: unable to get IRQ from DT, %d\n", irq);
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+ return -EINVAL;
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+ }
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+
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+ big_endian = of_property_read_bool(np, "big-endian");
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+
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+ ret = devm_request_irq(&pdev->dev, irq, ftm_alarm_interrupt,
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+ IRQF_NO_SUSPEND, dev_name(&pdev->dev), NULL);
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+ if (ret < 0) {
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+ dev_err(&pdev->dev, "failed to request irq\n");
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+ return ret;
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+ }
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+
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+ ret = device_create_file(&pdev->dev, &ftm_alarm_attributes);
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+ if (ret) {
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+ dev_err(&pdev->dev, "create sysfs fail.\n");
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+ return ret;
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+ }
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+
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+ alarm_freq = (u32)FIXED_FREQ_CLK / (u32)MAX_FREQ_DIV;
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+
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+ ftm_clean_alarm();
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+
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+ device_init_wakeup(&pdev->dev, true);
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+
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+ return ret;
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+}
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+
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+static const struct of_device_id ftm_alarm_match[] = {
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+ { .compatible = "fsl,ftm-alarm", },
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+ { .compatible = "fsl,ls1012a-ftm-alarm", },
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+ { .compatible = "fsl,ls1021a-ftm-alarm", },
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+ { .compatible = "fsl,ls1043a-ftm-alarm", },
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+ { .compatible = "fsl,ls1046a-ftm-alarm", },
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+ { .compatible = "fsl,ls1088a-ftm-alarm", },
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+ { .compatible = "fsl,ls208xa-ftm-alarm", },
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+ { .compatible = "fsl,lx2160a-ftm-alarm", },
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+ { .compatible = "fsl,ftm-timer", },
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+ { },
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+};
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+
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+static struct platform_driver ftm_alarm_driver = {
|
|
+ .probe = ftm_alarm_probe,
|
|
+ .driver = {
|
|
+ .name = "ftm-alarm",
|
|
+ .owner = THIS_MODULE,
|
|
+ .of_match_table = ftm_alarm_match,
|
|
+ },
|
|
+};
|
|
+
|
|
+static int __init ftm_alarm_init(void)
|
|
+{
|
|
+ return platform_driver_register(&ftm_alarm_driver);
|
|
+}
|
|
+device_initcall(ftm_alarm_init);
|