184 lines
7.4 KiB
Diff
184 lines
7.4 KiB
Diff
From 86e03654997db1b70e71f717ab3e74b1df2f402c Mon Sep 17 00:00:00 2001
|
|
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
|
Date: Thu, 13 Jul 2017 18:28:27 +0800
|
|
Subject: [PATCH] arm64: dts: freescale: lx2160a: add pcie DT nodes
|
|
|
|
The LX2160A integrated 6 PCIe Gen4 controllers.
|
|
|
|
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
|
---
|
|
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 162 +++++++++++++++++++++++++
|
|
1 file changed, 162 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
|
|
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
|
|
@@ -903,6 +903,168 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ pcie@3400000 {
|
|
+ compatible = "fsl,lx2160a-pcie";
|
|
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
|
+ 0x80 0x00000000 0x0 0x00001000>; /* configuration space */
|
|
+ reg-names = "csr_axi_slave", "config_axi_slave";
|
|
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
|
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
|
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
|
+ interrupt-names = "aer", "pme", "intr";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ dma-coherent;
|
|
+ apio-wins = <8>;
|
|
+ ppio-wins = <8>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&its>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@3500000 {
|
|
+ compatible = "fsl,lx2160a-pcie";
|
|
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
|
+ 0x88 0x00000000 0x0 0x00001000>; /* configuration space */
|
|
+ reg-names = "csr_axi_slave", "config_axi_slave";
|
|
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
|
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
|
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
|
+ interrupt-names = "aer", "pme", "intr";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ dma-coherent;
|
|
+ apio-wins = <8>;
|
|
+ ppio-wins = <8>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&its>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@3600000 {
|
|
+ compatible = "fsl,lx2160a-pcie";
|
|
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
|
+ 0x90 0x00000000 0x0 0x00001000>; /* configuration space */
|
|
+ reg-names = "csr_axi_slave", "config_axi_slave";
|
|
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
|
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
|
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
|
+ interrupt-names = "aer", "pme", "intr";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ dma-coherent;
|
|
+ apio-wins = <8>;
|
|
+ ppio-wins = <8>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&its>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@3700000 {
|
|
+ compatible = "fsl,lx2160a-pcie";
|
|
+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
|
|
+ 0x98 0x00000000 0x0 0x00001000>; /* configuration space */
|
|
+ reg-names = "csr_axi_slave", "config_axi_slave";
|
|
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
|
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
|
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
|
+ interrupt-names = "aer", "pme", "intr";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ dma-coherent;
|
|
+ apio-wins = <8>;
|
|
+ ppio-wins = <8>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&its>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@3800000 {
|
|
+ compatible = "fsl,lx2160a-pcie";
|
|
+ reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
|
|
+ 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */
|
|
+ reg-names = "csr_axi_slave", "config_axi_slave";
|
|
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
|
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
|
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
|
+ interrupt-names = "aer", "pme", "intr";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ dma-coherent;
|
|
+ apio-wins = <8>;
|
|
+ ppio-wins = <8>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&its>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ pcie@3900000 {
|
|
+ compatible = "fsl,lx2160a-pcie";
|
|
+ reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
|
|
+ 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */
|
|
+ reg-names = "csr_axi_slave", "config_axi_slave";
|
|
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
|
|
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
|
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
|
|
+ interrupt-names = "aer", "pme", "intr";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ dma-coherent;
|
|
+ apio-wins = <8>;
|
|
+ ppio-wins = <8>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&its>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
+ <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
smmu: iommu@5000000 {
|
|
compatible = "arm,mmu-500";
|
|
reg = <0 0x5000000 0 0x800000>;
|