mirror of
git://git.openwrt.org/openwrt/openwrt.git
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87318eb179
Copy config and patch from 5.10 to 5.15 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
343 lines
10 KiB
C
343 lines
10 KiB
C
/*
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* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all copies.
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
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* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __AR40XX_H
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#define __AR40XX_H
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#define AR40XX_MAX_VLANS 128
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#define AR40XX_NUM_PORTS 6
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#define AR40XX_NUM_PHYS 5
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#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
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struct ar40xx_priv {
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struct switch_dev dev;
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u8 __iomem *hw_addr;
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u8 __iomem *psgmii_hw_addr;
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u32 mac_mode;
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struct reset_control *ess_rst;
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u32 cpu_bmp;
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u32 lan_bmp;
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u32 wan_bmp;
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struct mii_bus *mii_bus;
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struct phy_device *phy;
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/* mutex for qm task */
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struct mutex qm_lock;
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struct delayed_work qm_dwork;
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u32 port_link_up[AR40XX_NUM_PORTS];
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u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
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u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
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u32 phy_t_status;
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/* mutex for switch reg access */
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struct mutex reg_mutex;
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/* mutex for mib task */
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struct mutex mib_lock;
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struct delayed_work mib_work;
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int mib_next_port;
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u64 *mib_stats;
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char buf[2048];
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/* all fields below will be cleared on reset */
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bool vlan;
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u16 vlan_id[AR40XX_MAX_VLANS];
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u8 vlan_table[AR40XX_MAX_VLANS];
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u8 vlan_tagged;
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u16 pvid[AR40XX_NUM_PORTS];
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/* mirror */
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bool mirror_rx;
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bool mirror_tx;
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int source_port;
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int monitor_port;
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};
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#define AR40XX_PORT_LINK_UP 1
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#define AR40XX_PORT_LINK_DOWN 0
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#define AR40XX_QM_NOT_EMPTY 1
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#define AR40XX_QM_EMPTY 0
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#define AR40XX_LAN_VLAN 1
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#define AR40XX_WAN_VLAN 2
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enum ar40xx_port_wrapper_cfg {
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PORT_WRAPPER_PSGMII = 0,
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};
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struct ar40xx_mib_desc {
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u32 size;
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u32 offset;
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const char *name;
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};
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#define AR40XX_PORT_CPU 0
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#define AR40XX_PSGMII_MODE_CONTROL 0x1b4
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#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
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#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
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#define AR40XX_MII_ATH_MMD_ADDR 0x0d
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#define AR40XX_MII_ATH_MMD_DATA 0x0e
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#define AR40XX_MII_ATH_DBG_ADDR 0x1d
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#define AR40XX_MII_ATH_DBG_DATA 0x1e
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#define AR40XX_STATS_RXBROAD 0x00
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#define AR40XX_STATS_RXPAUSE 0x04
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#define AR40XX_STATS_RXMULTI 0x08
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#define AR40XX_STATS_RXFCSERR 0x0c
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#define AR40XX_STATS_RXALIGNERR 0x10
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#define AR40XX_STATS_RXRUNT 0x14
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#define AR40XX_STATS_RXFRAGMENT 0x18
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#define AR40XX_STATS_RX64BYTE 0x1c
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#define AR40XX_STATS_RX128BYTE 0x20
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#define AR40XX_STATS_RX256BYTE 0x24
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#define AR40XX_STATS_RX512BYTE 0x28
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#define AR40XX_STATS_RX1024BYTE 0x2c
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#define AR40XX_STATS_RX1518BYTE 0x30
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#define AR40XX_STATS_RXMAXBYTE 0x34
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#define AR40XX_STATS_RXTOOLONG 0x38
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#define AR40XX_STATS_RXGOODBYTE 0x3c
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#define AR40XX_STATS_RXBADBYTE 0x44
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#define AR40XX_STATS_RXOVERFLOW 0x4c
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#define AR40XX_STATS_FILTERED 0x50
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#define AR40XX_STATS_TXBROAD 0x54
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#define AR40XX_STATS_TXPAUSE 0x58
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#define AR40XX_STATS_TXMULTI 0x5c
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#define AR40XX_STATS_TXUNDERRUN 0x60
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#define AR40XX_STATS_TX64BYTE 0x64
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#define AR40XX_STATS_TX128BYTE 0x68
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#define AR40XX_STATS_TX256BYTE 0x6c
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#define AR40XX_STATS_TX512BYTE 0x70
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#define AR40XX_STATS_TX1024BYTE 0x74
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#define AR40XX_STATS_TX1518BYTE 0x78
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#define AR40XX_STATS_TXMAXBYTE 0x7c
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#define AR40XX_STATS_TXOVERSIZE 0x80
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#define AR40XX_STATS_TXBYTE 0x84
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#define AR40XX_STATS_TXCOLLISION 0x8c
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#define AR40XX_STATS_TXABORTCOL 0x90
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#define AR40XX_STATS_TXMULTICOL 0x94
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#define AR40XX_STATS_TXSINGLECOL 0x98
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#define AR40XX_STATS_TXEXCDEFER 0x9c
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#define AR40XX_STATS_TXDEFER 0xa0
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#define AR40XX_STATS_TXLATECOL 0xa4
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#define AR40XX_REG_MODULE_EN 0x030
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#define AR40XX_MODULE_EN_MIB BIT(0)
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#define AR40XX_REG_MIB_FUNC 0x034
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#define AR40XX_MIB_BUSY BIT(17)
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#define AR40XX_MIB_CPU_KEEP BIT(20)
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#define AR40XX_MIB_FUNC BITS(24, 3)
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#define AR40XX_MIB_FUNC_S 24
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#define AR40XX_MIB_FUNC_NO_OP 0x0
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#define AR40XX_MIB_FUNC_FLUSH 0x1
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#define AR40XX_ESS_SERVICE_TAG 0x48
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#define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
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#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
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#define AR40XX_PORT_SPEED BITS(0, 2)
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#define AR40XX_PORT_STATUS_SPEED_S 0
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#define AR40XX_PORT_TX_EN BIT(2)
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#define AR40XX_PORT_RX_EN BIT(3)
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#define AR40XX_PORT_STATUS_TXFLOW BIT(4)
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#define AR40XX_PORT_STATUS_RXFLOW BIT(5)
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#define AR40XX_PORT_DUPLEX BIT(6)
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#define AR40XX_PORT_TXHALF_FLOW BIT(7)
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#define AR40XX_PORT_STATUS_LINK_UP BIT(8)
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#define AR40XX_PORT_AUTO_LINK_EN BIT(9)
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#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12)
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#define AR40XX_REG_MAX_FRAME_SIZE 0x078
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#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14)
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#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
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#define AR40XX_REG_EEE_CTRL 0x100
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#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
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#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
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#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12)
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#define AR40XX_PORT_VLAN0_DEF_SVID_S 0
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#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12)
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#define AR40XX_PORT_VLAN0_DEF_CVID_S 16
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#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
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#define AR40XX_PORT_VLAN1_CORE_PORT BIT(9)
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#define AR40XX_PORT_VLAN1_PORT_TLS_MODE BIT(7)
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#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
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#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2)
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#define AR40XX_PORT_VLAN1_OUT_MODE_S 12
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#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0
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#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1
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#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2
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#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3
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#define AR40XX_REG_VTU_FUNC0 0x0610
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#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14)
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#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
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#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0
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#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1
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#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2
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#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3
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#define AR40XX_VTU_FUNC0_IVL BIT(19)
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#define AR40XX_VTU_FUNC0_VALID BIT(20)
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#define AR40XX_REG_VTU_FUNC1 0x0614
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#define AR40XX_VTU_FUNC1_OP BITS(0, 3)
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#define AR40XX_VTU_FUNC1_OP_NOOP 0
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#define AR40XX_VTU_FUNC1_OP_FLUSH 1
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#define AR40XX_VTU_FUNC1_OP_LOAD 2
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#define AR40XX_VTU_FUNC1_OP_PURGE 3
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#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4
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#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5
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#define AR40XX7_VTU_FUNC1_OP_GET_ONE 6
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#define AR40XX_VTU_FUNC1_FULL BIT(4)
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#define AR40XX_VTU_FUNC1_PORT BIT(8, 4)
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#define AR40XX_VTU_FUNC1_PORT_S 8
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#define AR40XX_VTU_FUNC1_VID BIT(16, 12)
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#define AR40XX_VTU_FUNC1_VID_S 16
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#define AR40XX_VTU_FUNC1_BUSY BIT(31)
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#define AR40XX_REG_FWD_CTRL0 0x620
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#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10)
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#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
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#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4
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#define AR40XX_REG_FWD_CTRL1 0x624
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#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7)
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#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0
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#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7)
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#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8
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#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7)
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#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16
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#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7)
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#define AR40XX_FWD_CTRL1_IGMP_S 24
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#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
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#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7)
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#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2)
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#define AR40XX_PORT_LOOKUP_IN_MODE_S 8
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#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3)
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#define AR40XX_PORT_LOOKUP_STATE_S 16
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#define AR40XX_PORT_LOOKUP_LEARN BIT(20)
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#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21)
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#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
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#define AR40XX_REG_ATU_FUNC 0x60c
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#define AR40XX_ATU_FUNC_OP BITS(0, 4)
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#define AR40XX_ATU_FUNC_OP_NOOP 0x0
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#define AR40XX_ATU_FUNC_OP_FLUSH 0x1
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#define AR40XX_ATU_FUNC_OP_LOAD 0x2
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#define AR40XX_ATU_FUNC_OP_PURGE 0x3
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#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4
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#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5
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#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6
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#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7
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#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8
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#define AR40XX_ATU_FUNC_BUSY BIT(31)
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#define AR40XX_REG_QM_DEBUG_ADDR 0x820
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#define AR40XX_REG_QM_DEBUG_VALUE 0x824
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#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d
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#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e
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#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
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#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
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#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4)
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#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60
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#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90
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#define AR40XX_PHY_DEBUG_0 0
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#define AR40XX_PHY_MANU_CTRL_EN BIT(12)
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#define AR40XX_PHY_DEBUG_2 2
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#define AR40XX_PHY_SPEC_STATUS 0x11
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#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10)
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#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13)
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#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2)
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/* port forwarding state */
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enum {
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AR40XX_PORT_STATE_DISABLED = 0,
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AR40XX_PORT_STATE_BLOCK = 1,
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AR40XX_PORT_STATE_LISTEN = 2,
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AR40XX_PORT_STATE_LEARN = 3,
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AR40XX_PORT_STATE_FORWARD = 4
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};
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/* ingress 802.1q mode */
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enum {
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AR40XX_IN_PORT_ONLY = 0,
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AR40XX_IN_PORT_FALLBACK = 1,
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AR40XX_IN_VLAN_ONLY = 2,
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AR40XX_IN_SECURE = 3
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};
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/* egress 802.1q mode */
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enum {
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AR40XX_OUT_KEEP = 0,
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AR40XX_OUT_STRIP_VLAN = 1,
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AR40XX_OUT_ADD_VLAN = 2
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};
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/* port speed */
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enum {
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AR40XX_PORT_SPEED_10M = 0,
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AR40XX_PORT_SPEED_100M = 1,
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AR40XX_PORT_SPEED_1000M = 2,
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AR40XX_PORT_SPEED_ERR = 3,
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};
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#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */
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#define AR40XX_QM_WORK_DELAY 100
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#define AR40XX_MIB_FUNC_CAPTURE 0x3
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#define AR40XX_REG_PORT_STATS_START 0x1000
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#define AR40XX_REG_PORT_STATS_LEN 0x100
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#define AR40XX_PORTS_ALL 0x3f
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#define AR40XX_PSGMII_ID 5
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#define AR40XX_PSGMII_CALB_NUM 100
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#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d
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#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
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#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
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#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380
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#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280
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#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a
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#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb
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#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
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#define AR40XX_MALIBU_PHY_LAST_ADDR 4
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static inline struct ar40xx_priv *
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swdev_to_ar40xx(struct switch_dev *swdev)
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{
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return container_of(swdev, struct ar40xx_priv, dev);
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}
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#endif
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