416 lines
16 KiB
Diff
416 lines
16 KiB
Diff
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Transport; Thu, 28 May 2020 14:18:47 +0800
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From: <chuanjia.liu@mediatek.com>
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To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
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Subject: [PATCH v2 1/4] dt-bindings: PCI: Mediatek: Update PCIe binding
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Date: Thu, 28 May 2020 14:16:45 +0800
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Message-ID: <20200528061648.32078-2-chuanjia.liu@mediatek.com>
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Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
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srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
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linux-mediatek-bounces+patchwork-linux-mediatek=patchwork.kernel.org@lists.infradead.org
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From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
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There are two independent PCIe controllers in MT2712/MT7622 platform,
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and each of them should contain an independent MSI domain.
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In current architecture, MSI domain will be inherited from the root
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bridge, and all of the devices will share the same MSI domain.
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Hence that, the PCIe devices will not work properly if the irq number
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which required is more than 32.
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Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
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comply with the hardware design.
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Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
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---
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.../bindings/pci/mediatek-pcie-cfg.yaml | 38 +++++
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.../devicetree/bindings/pci/mediatek-pcie.txt | 144 +++++++++++-------
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2 files changed, 129 insertions(+), 53 deletions(-)
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create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
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@@ -0,0 +1,38 @@
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/pci/mediatek-pcie-cfg.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Mediatek PCIECFG controller
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+
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+maintainers:
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+ - Chuanjia Liu <chuanjia.liu@mediatek.com>
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+ - Jianjun Wang <jianjun.wang@mediatek.com>
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+
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+description: |
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+ The MediaTek PCIECFG controller controls some feature about
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+ LTSSM, ASPM and so on.
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+
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+properties:
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+ compatible:
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+ items:
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+ - enum:
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+ - mediatek,mt7622-pciecfg
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+ - mediatek,mt7629-pciecfg
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+ - const: syscon
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+
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+ reg:
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+ maxItems: 1
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+
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+required:
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+ - compatible
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+ - reg
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+
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+examples:
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+ - |
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+ pciecfg: pciecfg@1a140000 {
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+ compatible = "mediatek,mt7622-pciecfg", "syscon";
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+ reg = <0 0x1a140000 0 0x1000>;
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+ };
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+...
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--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
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+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
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@@ -8,7 +8,7 @@ Required properties:
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"mediatek,mt7623-pcie"
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"mediatek,mt7629-pcie"
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- device_type: Must be "pci"
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-- reg: Base addresses and lengths of the PCIe subsys and root ports.
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+- reg: Base addresses and lengths of the root ports.
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- reg-names: Names of the above areas to use during resource lookup.
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- #address-cells: Address representation for root ports (must be 3)
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- #size-cells: Size representation for root ports (must be 2)
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@@ -19,10 +19,10 @@ Required properties:
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- sys_ckN :transaction layer and data link layer clock
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Required entries for MT2701/MT7623:
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- free_ck :for reference clock of PCIe subsys
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- Required entries for MT2712/MT7622:
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+ Required entries for MT2712/MT7622/MT7629:
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- ahb_ckN :AHB slave interface operating clock for CSR access and RC
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initiated MMIO access
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- Required entries for MT7622:
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+ Required entries for MT7622/MT7629:
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- axi_ckN :application layer MMIO channel operating clock
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- aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
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pcie_mac_ck/pcie_pipe_ck is turned off
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@@ -47,10 +47,13 @@ Required properties for MT7623/MT2701:
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- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
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number of root ports.
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-Required properties for MT2712/MT7622:
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+Required properties for MT2712/MT7622/MT7629:
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-interrupts: A list of interrupt outputs of the controller, must have one
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entry for each PCIe port
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+Required properties for MT7622/MT7629:
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+- mediatek,pcie-subsys: Should be a phandle of the pciecfg node.
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+
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In addition, the device tree node must have sub-nodes describing each
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PCIe port interface, having the following mandatory properties:
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@@ -143,56 +146,73 @@ Examples for MT7623:
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Examples for MT2712:
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- pcie: pcie@11700000 {
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+ pcie1: pcie@112ff000 {
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compatible = "mediatek,mt2712-pcie";
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device_type = "pci";
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- reg = <0 0x11700000 0 0x1000>,
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- <0 0x112ff000 0 0x1000>;
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- reg-names = "port0", "port1";
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+ reg = <0 0x112ff000 0 0x1000>;
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+ reg-names = "port1";
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#address-cells = <3>;
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#size-cells = <2>;
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- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
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- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
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- <&pericfg CLK_PERI_PCIE0>,
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+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pcie_irq";
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+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
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<&pericfg CLK_PERI_PCIE1>;
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- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
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- phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
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- phy-names = "pcie-phy0", "pcie-phy1";
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+ clock-names = "sys_ck1", "ahb_ck1";
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+ phys = <&u3port1 PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy1";
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bus-range = <0x00 0xff>;
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- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
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+ status = "disabled";
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- pcie0: pcie@0,0 {
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- reg = <0x0000 0 0 0 0>;
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+ slot1: pcie@1,0 {
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+ reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 7>;
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- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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- <0 0 0 2 &pcie_intc0 1>,
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- <0 0 0 3 &pcie_intc0 2>,
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- <0 0 0 4 &pcie_intc0 3>;
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- pcie_intc0: interrupt-controller {
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+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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+ <0 0 0 2 &pcie_intc1 1>,
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+ <0 0 0 3 &pcie_intc1 2>,
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+ <0 0 0 4 &pcie_intc1 3>;
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+ pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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+ };
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- pcie1: pcie@1,0 {
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- reg = <0x0800 0 0 0 0>;
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+ pcie0: pcie@11700000 {
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+ compatible = "mediatek,mt2712-pcie";
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+ device_type = "pci";
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+ reg = <0 0x11700000 0 0x1000>;
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+ reg-names = "port0";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pcie_irq";
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+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
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+ <&pericfg CLK_PERI_PCIE0>;
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+ clock-names = "sys_ck0", "ahb_ck0";
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+ phys = <&u3port0 PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy0";
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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+ status = "disabled";
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+
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+ slot0: pcie@0,0 {
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+ reg = <0x0000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 7>;
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- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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- <0 0 0 2 &pcie_intc1 1>,
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- <0 0 0 3 &pcie_intc1 2>,
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- <0 0 0 4 &pcie_intc1 3>;
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- pcie_intc1: interrupt-controller {
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+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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+ <0 0 0 2 &pcie_intc0 1>,
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+ <0 0 0 3 &pcie_intc0 2>,
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+ <0 0 0 4 &pcie_intc0 3>;
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+ pcie_intc0: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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@@ -202,39 +222,31 @@ Examples for MT2712:
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Examples for MT7622:
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- pcie: pcie@1a140000 {
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+ pcie0: pcie@1a143000 {
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compatible = "mediatek,mt7622-pcie";
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device_type = "pci";
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- reg = <0 0x1a140000 0 0x1000>,
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- <0 0x1a143000 0 0x1000>,
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- <0 0x1a145000 0 0x1000>;
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- reg-names = "subsys", "port0", "port1";
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+ reg = <0 0x1a143000 0 0x1000>;
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+ reg-names = "port0";
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+ mediatek,pcie-cfg = <&pciecfg>;
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#address-cells = <3>;
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#size-cells = <2>;
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- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
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- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
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+ interrupt-names = "pcie_irq";
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clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
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- <&pciesys CLK_PCIE_P1_MAC_EN>,
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<&pciesys CLK_PCIE_P0_AHB_EN>,
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- <&pciesys CLK_PCIE_P1_AHB_EN>,
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<&pciesys CLK_PCIE_P0_AUX_EN>,
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- <&pciesys CLK_PCIE_P1_AUX_EN>,
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<&pciesys CLK_PCIE_P0_AXI_EN>,
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- <&pciesys CLK_PCIE_P1_AXI_EN>,
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<&pciesys CLK_PCIE_P0_OBFF_EN>,
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- <&pciesys CLK_PCIE_P1_OBFF_EN>,
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- <&pciesys CLK_PCIE_P0_PIPE_EN>,
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- <&pciesys CLK_PCIE_P1_PIPE_EN>;
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- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
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- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
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- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
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- phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
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- phy-names = "pcie-phy0", "pcie-phy1";
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+ <&pciesys CLK_PCIE_P0_PIPE_EN>;
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+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
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+ "axi_ck0", "obff_ck0", "pipe_ck0";
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+
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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bus-range = <0x00 0xff>;
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- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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+ ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x8000000>;
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+ status = "disabled";
|
|
|
|
- pcie0: pcie@0,0 {
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+ slot0: pcie@0,0 {
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reg = <0x0000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
@@ -251,8 +263,34 @@ Examples for MT7622:
|
|
#interrupt-cells = <1>;
|
|
};
|
|
};
|
|
+ };
|
|
+
|
|
+ pcie1: pcie@1a145000 {
|
|
+ compatible = "mediatek,mt7622-pcie";
|
|
+ device_type = "pci";
|
|
+ reg = <0 0x1a145000 0 0x1000>;
|
|
+ reg-names = "port1";
|
|
+ mediatek,pcie-cfg = <&pciecfg>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
|
|
+ interrupt-names = "pcie_irq";
|
|
+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
|
|
+ /* designer has connect RC1 with p0_ahb clock */
|
|
+ <&pciesys CLK_PCIE_P0_AHB_EN>,
|
|
+ <&pciesys CLK_PCIE_P1_AUX_EN>,
|
|
+ <&pciesys CLK_PCIE_P1_AXI_EN>,
|
|
+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
|
|
+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
|
|
+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
|
|
+ "axi_ck1", "obff_ck1", "pipe_ck1";
|
|
+
|
|
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
|
|
+ bus-range = <0x00 0xff>;
|
|
+ ranges = <0x82000000 0 0x28000000 0 0x28000000 0 0x8000000>;
|
|
+ status = "disabled";
|
|
|
|
- pcie1: pcie@1,0 {
|
|
+ slot1: pcie@1,0 {
|
|
reg = <0x0800 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|