696 lines
19 KiB
Diff
696 lines
19 KiB
Diff
From d2d2489e0a4b740abd980e9d1cad952d15bc2d9e Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sun, 30 Nov 2014 14:55:02 +0100
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Subject: [PATCH] MIPS: BCM63XX: switch to IRQ_DOMAIN
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Now that we have working IRQ_DOMAIN drivers for both interrupt controllers,
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switch to using them.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/Kconfig | 3 +
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arch/mips/bcm63xx/irq.c | 612 +++++++++---------------------------------------
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2 files changed, 108 insertions(+), 507 deletions(-)
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -292,6 +292,9 @@ config BCM63XX
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select SYNC_R4K
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select DMA_NONCOHERENT
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select IRQ_MIPS_CPU
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+ select BCM6345_EXT_IRQ
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+ select BCM6345_PERIPH_IRQ
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+ select IRQ_DOMAIN
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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--- a/arch/mips/bcm63xx/irq.c
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+++ b/arch/mips/bcm63xx/irq.c
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@@ -11,7 +11,9 @@
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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-#include <linux/spinlock.h>
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+#include <linux/irqchip.h>
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+#include <linux/irqchip/irq-bcm6345-ext.h>
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+#include <linux/irqchip/irq-bcm6345-periph.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <bcm63xx_cpu.h>
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@@ -19,544 +21,140 @@
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#include <bcm63xx_io.h>
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#include <bcm63xx_irq.h>
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-
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-static DEFINE_SPINLOCK(ipic_lock);
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-static DEFINE_SPINLOCK(epic_lock);
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-
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-static u32 irq_stat_addr[2];
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-static u32 irq_mask_addr[2];
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-static void (*dispatch_internal)(int cpu);
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-static int is_ext_irq_cascaded;
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-static unsigned int ext_irq_count;
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-static unsigned int ext_irq_start, ext_irq_end;
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-static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
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-static void (*internal_irq_mask)(struct irq_data *d);
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-static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m);
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-
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-
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-static inline u32 get_ext_irq_perf_reg(int irq)
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-{
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- if (irq < 4)
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- return ext_irq_cfg_reg1;
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- return ext_irq_cfg_reg2;
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-}
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-
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-static inline void handle_internal(int intbit)
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-{
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- if (is_ext_irq_cascaded &&
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- intbit >= ext_irq_start && intbit <= ext_irq_end)
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- do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
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- else
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- do_IRQ(intbit + IRQ_INTERNAL_BASE);
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-}
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-
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-static inline int enable_irq_for_cpu(int cpu, struct irq_data *d,
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- const struct cpumask *m)
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-{
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- bool enable = cpu_online(cpu);
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-
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-#ifdef CONFIG_SMP
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- if (m)
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- enable &= cpumask_test_cpu(cpu, m);
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- else if (irqd_affinity_was_set(d))
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- enable &= cpumask_test_cpu(cpu, irq_data_get_affinity_mask(d));
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-#endif
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- return enable;
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-}
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-
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-/*
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- * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
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- * prioritize any interrupt relatively to another. the static counter
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- * will resume the loop where it ended the last time we left this
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- * function.
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- */
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-
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-#define BUILD_IPIC_INTERNAL(width) \
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-void __dispatch_internal_##width(int cpu) \
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-{ \
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- u32 pending[width / 32]; \
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- unsigned int src, tgt; \
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- bool irqs_pending = false; \
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- static unsigned int i[2]; \
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- unsigned int *next = &i[cpu]; \
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- unsigned long flags; \
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- \
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- /* read registers in reverse order */ \
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- spin_lock_irqsave(&ipic_lock, flags); \
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- for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
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- u32 val; \
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- \
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- val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \
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- val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \
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- pending[--tgt] = val; \
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- \
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- if (val) \
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- irqs_pending = true; \
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- } \
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- spin_unlock_irqrestore(&ipic_lock, flags); \
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- \
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- if (!irqs_pending) \
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- return; \
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- \
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- while (1) { \
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- unsigned int to_call = *next; \
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- \
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- *next = (*next + 1) & (width - 1); \
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- if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \
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- handle_internal(to_call); \
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- break; \
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- } \
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- } \
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-} \
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- \
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-static void __internal_irq_mask_##width(struct irq_data *d) \
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-{ \
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- u32 val; \
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- unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
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- unsigned reg = (irq / 32) ^ (width/32 - 1); \
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- unsigned bit = irq & 0x1f; \
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- unsigned long flags; \
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- int cpu; \
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- \
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- spin_lock_irqsave(&ipic_lock, flags); \
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- for_each_present_cpu(cpu) { \
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- if (!irq_mask_addr[cpu]) \
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- break; \
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- \
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- val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
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- val &= ~(1 << bit); \
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- bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
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- } \
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- spin_unlock_irqrestore(&ipic_lock, flags); \
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-} \
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- \
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-static void __internal_irq_unmask_##width(struct irq_data *d, \
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- const struct cpumask *m) \
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-{ \
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- u32 val; \
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- unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
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- unsigned reg = (irq / 32) ^ (width/32 - 1); \
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- unsigned bit = irq & 0x1f; \
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- unsigned long flags; \
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- int cpu; \
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- \
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- spin_lock_irqsave(&ipic_lock, flags); \
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- for_each_present_cpu(cpu) { \
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- if (!irq_mask_addr[cpu]) \
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- break; \
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- \
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- val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
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- if (enable_irq_for_cpu(cpu, d, m)) \
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- val |= (1 << bit); \
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- else \
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- val &= ~(1 << bit); \
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- bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
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- } \
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- spin_unlock_irqrestore(&ipic_lock, flags); \
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-}
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-
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-BUILD_IPIC_INTERNAL(32);
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-BUILD_IPIC_INTERNAL(64);
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-
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-asmlinkage void plat_irq_dispatch(void)
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-{
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- u32 cause;
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-
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- do {
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- cause = read_c0_cause() & read_c0_status() & ST0_IM;
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-
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- if (!cause)
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- break;
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-
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- if (cause & CAUSEF_IP7)
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- do_IRQ(7);
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- if (cause & CAUSEF_IP0)
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- do_IRQ(0);
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- if (cause & CAUSEF_IP1)
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- do_IRQ(1);
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- if (cause & CAUSEF_IP2)
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- dispatch_internal(0);
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- if (is_ext_irq_cascaded) {
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- if (cause & CAUSEF_IP3)
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- dispatch_internal(1);
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- } else {
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- if (cause & CAUSEF_IP3)
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- do_IRQ(IRQ_EXT_0);
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- if (cause & CAUSEF_IP4)
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- do_IRQ(IRQ_EXT_1);
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- if (cause & CAUSEF_IP5)
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- do_IRQ(IRQ_EXT_2);
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- if (cause & CAUSEF_IP6)
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- do_IRQ(IRQ_EXT_3);
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- }
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- } while (1);
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-}
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-
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-/*
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- * internal IRQs operations: only mask/unmask on PERF irq mask
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- * register.
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- */
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-static void bcm63xx_internal_irq_mask(struct irq_data *d)
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-{
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- internal_irq_mask(d);
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-}
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-
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-static void bcm63xx_internal_irq_unmask(struct irq_data *d)
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-{
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- internal_irq_unmask(d, NULL);
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-}
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-
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-/*
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- * external IRQs operations: mask/unmask and clear on PERF external
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- * irq control register.
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- */
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-static void bcm63xx_external_irq_mask(struct irq_data *d)
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-{
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- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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- u32 reg, regaddr;
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- unsigned long flags;
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-
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- regaddr = get_ext_irq_perf_reg(irq);
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- spin_lock_irqsave(&epic_lock, flags);
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- reg = bcm_perf_readl(regaddr);
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-
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- if (BCMCPU_IS_6348())
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- reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
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- else
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- reg &= ~EXTIRQ_CFG_MASK(irq % 4);
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-
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- bcm_perf_writel(reg, regaddr);
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- spin_unlock_irqrestore(&epic_lock, flags);
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-
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- if (is_ext_irq_cascaded)
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- internal_irq_mask(irq_get_irq_data(irq + ext_irq_start));
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-}
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-
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-static void bcm63xx_external_irq_unmask(struct irq_data *d)
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-{
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- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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- u32 reg, regaddr;
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- unsigned long flags;
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-
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- regaddr = get_ext_irq_perf_reg(irq);
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- spin_lock_irqsave(&epic_lock, flags);
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- reg = bcm_perf_readl(regaddr);
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-
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- if (BCMCPU_IS_6348())
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- reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
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- else
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- reg |= EXTIRQ_CFG_MASK(irq % 4);
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-
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- bcm_perf_writel(reg, regaddr);
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- spin_unlock_irqrestore(&epic_lock, flags);
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-
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- if (is_ext_irq_cascaded)
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- internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start),
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- NULL);
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-}
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-
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-static void bcm63xx_external_irq_clear(struct irq_data *d)
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-{
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- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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- u32 reg, regaddr;
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- unsigned long flags;
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-
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- regaddr = get_ext_irq_perf_reg(irq);
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- spin_lock_irqsave(&epic_lock, flags);
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- reg = bcm_perf_readl(regaddr);
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-
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- if (BCMCPU_IS_6348())
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- reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
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- else
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- reg |= EXTIRQ_CFG_CLEAR(irq % 4);
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-
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- bcm_perf_writel(reg, regaddr);
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- spin_unlock_irqrestore(&epic_lock, flags);
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-}
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-
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-static int bcm63xx_external_irq_set_type(struct irq_data *d,
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- unsigned int flow_type)
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-{
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- unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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- u32 reg, regaddr;
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- int levelsense, sense, bothedge;
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- unsigned long flags;
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-
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- flow_type &= IRQ_TYPE_SENSE_MASK;
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-
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- if (flow_type == IRQ_TYPE_NONE)
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- flow_type = IRQ_TYPE_LEVEL_LOW;
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-
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- levelsense = sense = bothedge = 0;
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- switch (flow_type) {
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- case IRQ_TYPE_EDGE_BOTH:
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- bothedge = 1;
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- break;
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-
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- case IRQ_TYPE_EDGE_RISING:
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- sense = 1;
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- break;
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-
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- case IRQ_TYPE_EDGE_FALLING:
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- break;
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-
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- case IRQ_TYPE_LEVEL_HIGH:
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- levelsense = 1;
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- sense = 1;
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- break;
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-
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- case IRQ_TYPE_LEVEL_LOW:
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- levelsense = 1;
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- break;
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-
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- default:
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- pr_err("bogus flow type combination given !\n");
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- return -EINVAL;
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- }
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-
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- regaddr = get_ext_irq_perf_reg(irq);
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- spin_lock_irqsave(&epic_lock, flags);
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- reg = bcm_perf_readl(regaddr);
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- irq %= 4;
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-
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- switch (bcm63xx_get_cpu_id()) {
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- case BCM6348_CPU_ID:
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- if (levelsense)
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- reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
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- else
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- reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
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- if (sense)
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- reg |= EXTIRQ_CFG_SENSE_6348(irq);
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- else
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- reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
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- if (bothedge)
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- reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
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- else
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- reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
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- break;
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-
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- case BCM3368_CPU_ID:
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- case BCM6328_CPU_ID:
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- case BCM6338_CPU_ID:
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- case BCM6345_CPU_ID:
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- case BCM6358_CPU_ID:
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- case BCM6362_CPU_ID:
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- case BCM6368_CPU_ID:
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- if (levelsense)
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- reg |= EXTIRQ_CFG_LEVELSENSE(irq);
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- else
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- reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
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- if (sense)
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- reg |= EXTIRQ_CFG_SENSE(irq);
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- else
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- reg &= ~EXTIRQ_CFG_SENSE(irq);
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- if (bothedge)
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- reg |= EXTIRQ_CFG_BOTHEDGE(irq);
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- else
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- reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
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- break;
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- default:
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- BUG();
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- }
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-
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- bcm_perf_writel(reg, regaddr);
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- spin_unlock_irqrestore(&epic_lock, flags);
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-
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- irqd_set_trigger_type(d, flow_type);
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- if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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- irq_set_handler_locked(d, handle_level_irq);
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- else
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- irq_set_handler_locked(d, handle_edge_irq);
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-
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- return IRQ_SET_MASK_OK_NOCOPY;
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-}
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-
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-#ifdef CONFIG_SMP
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-static int bcm63xx_internal_set_affinity(struct irq_data *data,
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- const struct cpumask *dest,
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- bool force)
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-{
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- if (!irqd_irq_disabled(data))
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- internal_irq_unmask(data, dest);
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-
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- return 0;
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-}
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-#endif
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-
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-static struct irq_chip bcm63xx_internal_irq_chip = {
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- .name = "bcm63xx_ipic",
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- .irq_mask = bcm63xx_internal_irq_mask,
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- .irq_unmask = bcm63xx_internal_irq_unmask,
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-};
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-
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-static struct irq_chip bcm63xx_external_irq_chip = {
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- .name = "bcm63xx_epic",
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- .irq_ack = bcm63xx_external_irq_clear,
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-
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- .irq_mask = bcm63xx_external_irq_mask,
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- .irq_unmask = bcm63xx_external_irq_unmask,
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-
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- .irq_set_type = bcm63xx_external_irq_set_type,
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-};
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-
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-static struct irqaction cpu_ip2_cascade_action = {
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- .handler = no_action,
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- .name = "cascade_ip2",
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- .flags = IRQF_NO_THREAD,
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-};
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-
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-#ifdef CONFIG_SMP
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-static struct irqaction cpu_ip3_cascade_action = {
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- .handler = no_action,
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- .name = "cascade_ip3",
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- .flags = IRQF_NO_THREAD,
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-};
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-#endif
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-
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-static struct irqaction cpu_ext_cascade_action = {
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- .handler = no_action,
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- .name = "cascade_extirq",
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- .flags = IRQF_NO_THREAD,
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-};
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-
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-static void bcm63xx_init_irq(void)
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+void __init arch_init_irq(void)
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{
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- int irq_bits;
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-
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- irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
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- irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
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- irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF);
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- irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF);
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+ void __iomem *periph_bases[2];
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+ void __iomem *ext_intc_bases[2];
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+ int periph_irq_count, periph_width, ext_irq_count, ext_shift;
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+ int periph_irqs[2] = { 2, 3 };
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+ int ext_irqs[6];
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+
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+ periph_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
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+ periph_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
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+ ext_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
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+ ext_intc_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
|
|
|
|
switch (bcm63xx_get_cpu_id()) {
|
|
case BCM3368_CPU_ID:
|
|
- irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
|
|
- irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
|
|
- irq_stat_addr[1] = 0;
|
|
- irq_mask_addr[1] = 0;
|
|
- irq_bits = 32;
|
|
- ext_irq_count = 4;
|
|
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
|
|
+ periph_bases[0] += PERF_IRQMASK_3368_REG;
|
|
+ periph_irq_count = 1;
|
|
+ periph_width = 1;
|
|
+
|
|
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_3368;
|
|
+ ext_irq_count = 4;
|
|
+ ext_irqs[0] = BCM_3368_EXT_IRQ0;
|
|
+ ext_irqs[1] = BCM_3368_EXT_IRQ1;
|
|
+ ext_irqs[2] = BCM_3368_EXT_IRQ2;
|
|
+ ext_irqs[3] = BCM_3368_EXT_IRQ3;
|
|
+ ext_shift = 4;
|
|
break;
|
|
case BCM6328_CPU_ID:
|
|
- irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
|
|
- irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
|
|
- irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1);
|
|
- irq_mask_addr[1] += PERF_IRQMASK_6328_REG(1);
|
|
- irq_bits = 64;
|
|
- ext_irq_count = 4;
|
|
- is_ext_irq_cascaded = 1;
|
|
- ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
|
|
- ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
|
|
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
|
|
+ periph_bases[0] += PERF_IRQMASK_6328_REG(0);
|
|
+ periph_bases[1] += PERF_IRQMASK_6328_REG(1);
|
|
+ periph_irq_count = 2;
|
|
+ periph_width = 2;
|
|
+
|
|
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6328;
|
|
+ ext_irq_count = 4;
|
|
+ ext_irqs[0] = BCM_6328_EXT_IRQ0;
|
|
+ ext_irqs[1] = BCM_6328_EXT_IRQ1;
|
|
+ ext_irqs[2] = BCM_6328_EXT_IRQ2;
|
|
+ ext_irqs[3] = BCM_6328_EXT_IRQ3;
|
|
+ ext_shift = 4;
|
|
break;
|
|
case BCM6338_CPU_ID:
|
|
- irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
|
|
- irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
|
|
- irq_stat_addr[1] = 0;
|
|
- irq_mask_addr[1] = 0;
|
|
- irq_bits = 32;
|
|
- ext_irq_count = 4;
|
|
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
|
|
+ periph_bases[0] += PERF_IRQMASK_6338_REG;
|
|
+ periph_irq_count = 1;
|
|
+ periph_width = 1;
|
|
+
|
|
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6338;
|
|
+ ext_irq_count = 4;
|
|
+ ext_irqs[0] = 3;
|
|
+ ext_irqs[1] = 4;
|
|
+ ext_irqs[2] = 5;
|
|
+ ext_irqs[3] = 6;
|
|
+ ext_shift = 4;
|
|
break;
|
|
case BCM6345_CPU_ID:
|
|
- irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
|
|
- irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
|
|
- irq_stat_addr[1] = 0;
|
|
- irq_mask_addr[1] = 0;
|
|
- irq_bits = 32;
|
|
- ext_irq_count = 4;
|
|
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
|
|
+ periph_bases[0] += PERF_IRQMASK_6345_REG;
|
|
+ periph_irq_count = 1;
|
|
+ periph_width = 1;
|
|
+
|
|
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6345;
|
|
+ ext_irq_count = 4;
|
|
+ ext_irqs[0] = 3;
|
|
+ ext_irqs[1] = 4;
|
|
+ ext_irqs[2] = 5;
|
|
+ ext_irqs[3] = 6;
|
|
+ ext_shift = 4;
|
|
break;
|
|
case BCM6348_CPU_ID:
|
|
- irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
|
|
- irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
|
|
- irq_stat_addr[1] = 0;
|
|
- irq_mask_addr[1] = 0;
|
|
- irq_bits = 32;
|
|
- ext_irq_count = 4;
|
|
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
|
|
+ periph_bases[0] += PERF_IRQMASK_6348_REG;
|
|
+ periph_irq_count = 1;
|
|
+ periph_width = 1;
|
|
+
|
|
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6348;
|
|
+ ext_irq_count = 4;
|
|
+ ext_irqs[0] = 3;
|
|
+ ext_irqs[1] = 4;
|
|
+ ext_irqs[2] = 5;
|
|
+ ext_irqs[3] = 6;
|
|
+ ext_shift = 5;
|
|
break;
|
|
case BCM6358_CPU_ID:
|
|
- irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
|
|
- irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
|
|
- irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1);
|
|
- irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1);
|
|
- irq_bits = 32;
|
|
- ext_irq_count = 4;
|
|
- is_ext_irq_cascaded = 1;
|
|
- ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
|
|
- ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
|
|
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
|
|
+ periph_bases[0] += PERF_IRQMASK_6358_REG(0);
|
|
+ periph_bases[1] += PERF_IRQMASK_6358_REG(1);
|
|
+ periph_irq_count = 2;
|
|
+ periph_width = 1;
|
|
+
|
|
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358;
|
|
+ ext_irq_count = 4;
|
|
+ ext_irqs[0] = BCM_6358_EXT_IRQ0;
|
|
+ ext_irqs[1] = BCM_6358_EXT_IRQ1;
|
|
+ ext_irqs[2] = BCM_6358_EXT_IRQ2;
|
|
+ ext_irqs[3] = BCM_6358_EXT_IRQ3;
|
|
+ ext_shift = 4;
|
|
break;
|
|
case BCM6362_CPU_ID:
|
|
- irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
|
|
- irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
|
|
- irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1);
|
|
- irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1);
|
|
- irq_bits = 64;
|
|
- ext_irq_count = 4;
|
|
- is_ext_irq_cascaded = 1;
|
|
- ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
|
|
- ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
|
|
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
|
|
+ periph_bases[0] += PERF_IRQMASK_6362_REG(0);
|
|
+ periph_bases[1] += PERF_IRQMASK_6362_REG(1);
|
|
+ periph_irq_count = 2;
|
|
+ periph_width = 2;
|
|
+
|
|
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6362;
|
|
+ ext_irq_count = 4;
|
|
+ ext_irqs[0] = BCM_6362_EXT_IRQ0;
|
|
+ ext_irqs[1] = BCM_6362_EXT_IRQ1;
|
|
+ ext_irqs[2] = BCM_6362_EXT_IRQ2;
|
|
+ ext_irqs[3] = BCM_6362_EXT_IRQ3;
|
|
+ ext_shift = 4;
|
|
break;
|
|
case BCM6368_CPU_ID:
|
|
- irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
|
|
- irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
|
|
- irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1);
|
|
- irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1);
|
|
- irq_bits = 64;
|
|
+ periph_bases[0] += PERF_IRQMASK_6368_REG(0);
|
|
+ periph_bases[1] += PERF_IRQMASK_6368_REG(1);
|
|
+ periph_irq_count = 2;
|
|
+ periph_width = 2;
|
|
+
|
|
+ ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6368;
|
|
+ ext_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6368;
|
|
ext_irq_count = 6;
|
|
- is_ext_irq_cascaded = 1;
|
|
- ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
|
|
- ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
|
|
- ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
|
|
- ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
|
|
+ ext_irqs[0] = BCM_6368_EXT_IRQ0;
|
|
+ ext_irqs[1] = BCM_6368_EXT_IRQ1;
|
|
+ ext_irqs[2] = BCM_6368_EXT_IRQ2;
|
|
+ ext_irqs[3] = BCM_6368_EXT_IRQ3;
|
|
+ ext_irqs[4] = BCM_6368_EXT_IRQ4;
|
|
+ ext_irqs[5] = BCM_6368_EXT_IRQ5;
|
|
+ ext_shift = 4;
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
- if (irq_bits == 32) {
|
|
- dispatch_internal = __dispatch_internal_32;
|
|
- internal_irq_mask = __internal_irq_mask_32;
|
|
- internal_irq_unmask = __internal_irq_unmask_32;
|
|
- } else {
|
|
- dispatch_internal = __dispatch_internal_64;
|
|
- internal_irq_mask = __internal_irq_mask_64;
|
|
- internal_irq_unmask = __internal_irq_unmask_64;
|
|
- }
|
|
-}
|
|
-
|
|
-void __init arch_init_irq(void)
|
|
-{
|
|
- int i;
|
|
-
|
|
- bcm63xx_init_irq();
|
|
mips_cpu_irq_init();
|
|
- for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
|
|
- irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
|
|
- handle_level_irq);
|
|
-
|
|
- for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
|
|
- irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
|
|
- handle_edge_irq);
|
|
-
|
|
- if (!is_ext_irq_cascaded) {
|
|
- for (i = 3; i < 3 + ext_irq_count; ++i)
|
|
- setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
|
|
- }
|
|
-
|
|
- setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
|
|
-#ifdef CONFIG_SMP
|
|
- if (is_ext_irq_cascaded) {
|
|
- setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
|
|
- bcm63xx_internal_irq_chip.irq_set_affinity =
|
|
- bcm63xx_internal_set_affinity;
|
|
-
|
|
- cpumask_clear(irq_default_affinity);
|
|
- cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
|
|
- }
|
|
-#endif
|
|
+ bcm6345_periph_intc_init(periph_irq_count, periph_irqs, periph_bases,
|
|
+ periph_width);
|
|
+ bcm6345_ext_intc_init(4, ext_irqs, ext_intc_bases[0], ext_shift);
|
|
+ if (ext_irq_count > 4)
|
|
+ bcm6345_ext_intc_init(2, &ext_irqs[4], ext_intc_bases[1],
|
|
+ ext_shift);
|
|
}
|