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b40705b677
Revert to using the checked in `tbb_linux` image tool binary since building it drags in the rather big Crypto++ project. Cherry-pick the post-release UART fixes. Switch to AUTORELEASE while at it. Signed-off-by: Andre Heider <a.heider@gmail.com>
178 lines
5.6 KiB
Diff
178 lines
5.6 KiB
Diff
From 5a91c439cbeb1f64b8b9830de91efad5113d3c89 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Fri, 14 May 2021 15:52:11 +0200
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Subject: [PATCH] fix(plat/marvell/a3720/uart): fix UART parent clock rate
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determination
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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The UART code for the A3K platform assumes that UART parent clock rate
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is always 25 MHz. This is incorrect, because the xtal clock can also run
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at 40 MHz (this is board specific).
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The frequency of the xtal clock is determined by a value on a strapping
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pin during SOC reset. The code to determine this frequency is already in
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A3K's comphy driver.
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Move the get_ref_clk() function from the comphy driver to a separate
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file and use it for UART parent clock rate determination.
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
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---
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drivers/marvell/comphy/phy-comphy-3700.c | 24 +------------
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.../marvell/armada/a3k/common/plat_marvell.h | 2 ++
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.../marvell/armada/a3k/common/a3700_common.mk | 1 +
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.../armada/a3k/common/aarch64/a3700_clock.S | 35 +++++++++++++++++++
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.../armada/a3k/common/include/platform_def.h | 1 -
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.../armada/common/aarch64/marvell_helpers.S | 10 +++++-
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plat/marvell/armada/common/marvell_console.c | 1 +
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7 files changed, 49 insertions(+), 25 deletions(-)
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create mode 100644 plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
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--- a/drivers/marvell/comphy/phy-comphy-3700.c
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+++ b/drivers/marvell/comphy/phy-comphy-3700.c
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@@ -14,6 +14,7 @@
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#include <mvebu.h>
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#include <mvebu_def.h>
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+#include <plat_marvell.h>
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#include "phy-comphy-3700.h"
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#include "phy-comphy-common.h"
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@@ -29,15 +30,6 @@
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#define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000)
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#define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000)
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-/*
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- * Below address in used only for reading, therefore no problem with concurrent
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- * Linux access.
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- */
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-#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
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- #define MVEBU_XTAL_MODE_MASK BIT(9)
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- #define MVEBU_XTAL_MODE_OFFS 9
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- #define MVEBU_XTAL_CLOCK_25MHZ 0x0
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-
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struct sgmii_phy_init_data_fix {
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uint16_t addr;
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uint16_t value;
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@@ -125,20 +117,6 @@ static uint16_t sgmii_phy_init[512] = {
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0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
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};
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-/* returns reference clock in MHz (25 or 40) */
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-static uint32_t get_ref_clk(void)
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-{
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- uint32_t val;
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-
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- val = (mmio_read_32(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
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- MVEBU_XTAL_MODE_OFFS;
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-
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- if (val == MVEBU_XTAL_CLOCK_25MHZ)
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- return 25;
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- else
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- return 40;
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-}
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-
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/* PHY selector configures with corresponding modes */
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static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,
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uint32_t comphy_mode)
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--- a/include/plat/marvell/armada/a3k/common/plat_marvell.h
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+++ b/include/plat/marvell/armada/a3k/common/plat_marvell.h
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@@ -100,4 +100,6 @@ void plat_marvell_interconnect_enter_coh
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const mmap_region_t *plat_marvell_get_mmap(void);
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+uint32_t get_ref_clk(void);
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+
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#endif /* PLAT_MARVELL_H */
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--- a/plat/marvell/armada/a3k/common/a3700_common.mk
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+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
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@@ -38,6 +38,7 @@ PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/
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-I$/drivers/arm/gic/common/
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PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
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+ $(PLAT_COMMON_BASE)/aarch64/a3700_clock.S \
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$(MARVELL_DRV_BASE)/uart/a3700_console.S
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BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
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--- /dev/null
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+++ b/plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
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@@ -0,0 +1,35 @@
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+/*
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+ * Copyright (C) 2018 Marvell International Ltd.
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+ *
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+ * SPDX-License-Identifier: BSD-3-Clause
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+ * https://spdx.org/licenses
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+ */
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+
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+#include <asm_macros.S>
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+#include <platform_def.h>
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+
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+/*
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+ * Below address in used only for reading, therefore no problem with concurrent
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+ * Linux access.
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+ */
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+#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
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+ #define MVEBU_XTAL_MODE_MASK BIT(9)
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+
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+ /* -----------------------------------------------------
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+ * uint32_t get_ref_clk (void);
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+ *
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+ * returns reference clock in MHz (25 or 40)
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+ * -----------------------------------------------------
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+ */
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+.globl get_ref_clk
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+func get_ref_clk
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+ mov_imm x0, MVEBU_TEST_PIN_LATCH_N
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+ ldr w0, [x0]
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+ tst w0, #MVEBU_XTAL_MODE_MASK
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+ bne 40
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+ mov w0, #25
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+ ret
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+40:
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+ mov w0, #40
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+ ret
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+endfunc get_ref_clk
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--- a/plat/marvell/armada/a3k/common/include/platform_def.h
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+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
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@@ -164,7 +164,6 @@
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* PL011 related constants
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*/
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#define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x12000)
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-#define PLAT_MARVELL_UART_CLK_IN_HZ 25000000
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#define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
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#define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
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--- a/plat/marvell/armada/common/aarch64/marvell_helpers.S
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+++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S
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@@ -63,8 +63,16 @@ endfunc plat_marvell_calc_core_pos
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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- mov_imm x0, PLAT_MARVELL_UART_BASE
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+#ifdef PLAT_a3700
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+ mov x1, x30
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+ bl get_ref_clk
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+ mov x30, x1
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+ mov_imm x1, 1000000
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+ mul x1, x0, x1
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+#else
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mov_imm x1, PLAT_MARVELL_UART_CLK_IN_HZ
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+#endif
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+ mov_imm x0, PLAT_MARVELL_UART_BASE
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mov_imm x2, MARVELL_CONSOLE_BAUDRATE
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#ifdef PLAT_a3700
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b console_a3700_core_init
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--- a/plat/marvell/armada/common/marvell_console.c
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+++ b/plat/marvell/armada/common/marvell_console.c
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@@ -14,6 +14,7 @@
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#ifdef PLAT_a3700
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#include <drivers/marvell/uart/a3700_console.h>
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+#define PLAT_MARVELL_UART_CLK_IN_HZ (get_ref_clk() * 1000000)
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#define console_marvell_register console_a3700_register
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#else
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#include <drivers/ti/uart/uart_16550.h>
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