276 lines
7.3 KiB
Diff
276 lines
7.3 KiB
Diff
From: John Crispin <blogic@openwrt.org>
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Date: Mon, 4 Aug 2014 20:36:29 +0200
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Subject: [PATCH 2/2] GPIO: MIPS: ralink: add gpio driver for ralink SoC
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Add gpio driver for Ralink SoC. This driver makes the gpio core on
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RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/gpio/Kconfig | 8 ++
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drivers/gpio/Makefile | 1 +
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drivers/gpio/gpio-ralink.c | 230 +++++++++++++++++++++++++++++++++++++
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3 files changed, 239 insertions(+)
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create mode 100644 drivers/gpio/gpio-ralink.c
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--- a/drivers/gpio/Kconfig
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+++ b/drivers/gpio/Kconfig
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@@ -509,6 +509,14 @@ config GPIO_PXA
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help
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Say yes here to support the PXA GPIO device.
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+config GPIO_RALINK
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+ bool "Ralink GPIO Support"
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+ depends on SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620
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+ select GPIO_GENERIC
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+ select GPIOLIB_IRQCHIP
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+ help
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+ Say yes here to support the Ralink SoC GPIO device
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+
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config GPIO_RCAR
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tristate "Renesas R-Car and RZ/G GPIO support"
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depends on ARCH_RENESAS || COMPILE_TEST
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--- a/drivers/gpio/Makefile
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+++ b/drivers/gpio/Makefile
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@@ -130,6 +130,7 @@ obj-$(CONFIG_GPIO_PISOSR) += gpio-pisos
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obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
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obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o
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obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
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+obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
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obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o
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obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
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obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
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--- /dev/null
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+++ b/drivers/gpio/gpio-ralink.c
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@@ -0,0 +1,230 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/err.h>
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+#include <linux/gpio/driver.h>
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+#include <linux/interrupt.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/spinlock.h>
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+
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+enum ralink_gpio_reg {
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+ GPIO_REG_INT = 0,
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+ GPIO_REG_EDGE,
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+ GPIO_REG_RENA,
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+ GPIO_REG_FENA,
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+ GPIO_REG_DATA,
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+ GPIO_REG_DIR,
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+ GPIO_REG_POL,
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+ GPIO_REG_SET,
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+ GPIO_REG_RESET,
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+ GPIO_REG_TOGGLE,
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+ GPIO_REG_MAX
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+};
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+
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+struct ralink_gpio_chip {
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+ struct gpio_chip chip;
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+ u8 regs[GPIO_REG_MAX];
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+
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+ spinlock_t lock;
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+ void __iomem *membase;
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+ int gpio_irq;
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+
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+ u32 rising;
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+ u32 falling;
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+};
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+
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+static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
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+{
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+ iowrite32(val, rg->membase + rg->regs[reg]);
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+}
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+
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+static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
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+{
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+ return ioread32(rg->membase + rg->regs[reg]);
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+}
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+
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+static irqreturn_t ralink_gpio_irq_handler(int irq, void *data)
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+{
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+ struct gpio_chip *gc = data;
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+ struct ralink_gpio_chip *rg = gpiochip_get_data(gc);
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+ irqreturn_t ret = IRQ_NONE;
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+ unsigned long pending;
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+ int bit;
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+
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+ pending = rt_gpio_r32(rg, GPIO_REG_INT);
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+ for_each_set_bit(bit, &pending, rg->chip.ngpio) {
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+ generic_handle_domain_irq(gc->irq.domain, bit);
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+ rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
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+ ret |= IRQ_HANDLED;
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+ }
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+
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+ return ret;
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+}
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+
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+static void ralink_gpio_irq_unmask(struct irq_data *d)
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+{
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+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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+ struct ralink_gpio_chip *rg = gpiochip_get_data(gc);
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+ unsigned long flags;
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+ u32 rise, fall;
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+
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+ rise = rt_gpio_r32(rg, GPIO_REG_RENA);
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+ fall = rt_gpio_r32(rg, GPIO_REG_FENA);
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+
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+ spin_lock_irqsave(&rg->lock, flags);
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+ rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));
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+ rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));
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+ spin_unlock_irqrestore(&rg->lock, flags);
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+}
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+
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+static void ralink_gpio_irq_mask(struct irq_data *d)
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+{
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+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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+ struct ralink_gpio_chip *rg = gpiochip_get_data(gc);
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+ unsigned long flags;
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+ u32 rise, fall;
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+
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+ rise = rt_gpio_r32(rg, GPIO_REG_RENA);
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+ fall = rt_gpio_r32(rg, GPIO_REG_FENA);
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+
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+ spin_lock_irqsave(&rg->lock, flags);
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+ rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));
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+ rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));
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+ spin_unlock_irqrestore(&rg->lock, flags);
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+}
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+
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+static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
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+{
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+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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+ struct ralink_gpio_chip *rg = gpiochip_get_data(gc);
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+ u32 mask = BIT(d->hwirq);
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+
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+ if (type == IRQ_TYPE_PROBE) {
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+ if ((rg->rising | rg->falling) & mask)
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+ return 0;
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+
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+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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+ }
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+
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+ if (type & IRQ_TYPE_EDGE_RISING)
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+ rg->rising |= mask;
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+ else
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+ rg->rising &= ~mask;
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+
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+ if (type & IRQ_TYPE_EDGE_FALLING)
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+ rg->falling |= mask;
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+ else
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+ rg->falling &= ~mask;
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+
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+ return 0;
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+}
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+
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+static struct irq_chip ralink_gpio_irq_chip = {
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+ .name = "gpio-ralink",
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+ .irq_unmask = ralink_gpio_irq_unmask,
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+ .irq_mask = ralink_gpio_irq_mask,
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+ .irq_mask_ack = ralink_gpio_irq_mask,
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+ .irq_set_type = ralink_gpio_irq_type,
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+ .flags = IRQCHIP_IMMUTABLE,
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+ GPIOCHIP_IRQ_RESOURCE_HELPERS,
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+};
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+
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+static int ralink_gpio_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct device_node *np = dev->of_node;
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+ struct ralink_gpio_chip *rg;
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+ int ret;
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+
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+ rg = devm_kzalloc(dev, sizeof(struct ralink_gpio_chip), GFP_KERNEL);
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+ if (!rg)
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+ return -ENOMEM;
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+
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+ rg->membase = devm_platform_ioremap_resource(pdev, 0);
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+ if (IS_ERR(rg->membase))
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+ return PTR_ERR(rg->membase);
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+
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+ if (of_property_read_u8_array(np, "ralink,register-map",
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+ rg->regs, GPIO_REG_MAX)) {
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+ dev_err(dev, "failed to read register definition\n");
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+ return -EINVAL;
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+ }
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+
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+ spin_lock_init(&rg->lock);
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+
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+ ret = bgpio_init(&rg->chip, dev, 4,
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+ rg->membase + rg->regs[GPIO_REG_DATA],
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+ rg->membase + rg->regs[GPIO_REG_SET],
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+ rg->membase + rg->regs[GPIO_REG_RESET],
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+ rg->membase + rg->regs[GPIO_REG_DIR],
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+ NULL, 0);
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+ if (ret)
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+ return dev_err_probe(dev, ret, "bgpio_init() failed\n");
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+
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+ /* set polarity to low for all lines */
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+ rt_gpio_w32(rg, GPIO_REG_POL, 0);
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+
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+ rg->gpio_irq = platform_get_irq(pdev, 0);
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+ if (rg->gpio_irq < 0)
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+ return rg->gpio_irq;
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+
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+ if (rg->gpio_irq) {
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+ struct gpio_irq_chip *girq;
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+
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+ /*
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+ * Directly request the irq here instead of passing
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+ * a flow-handler because the irq is shared.
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+ */
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+ ret = devm_request_irq(dev, rg->gpio_irq,
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+ ralink_gpio_irq_handler, IRQF_SHARED,
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+ NULL, &rg->chip);
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+ if (ret) {
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+ dev_err(dev, "Error requesting IRQ %d: %d\n",
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+ rg->gpio_irq, ret);
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+ return ret;
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+ }
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+
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+ girq = &rg->chip.irq;
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+ gpio_irq_chip_set_chip(girq, &ralink_gpio_irq_chip);
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+ /* This will let us handle the parent IRQ in the driver */
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+ girq->parent_handler = NULL;
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+ girq->num_parents = 0;
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+ girq->parents = NULL;
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+ girq->default_type = IRQ_TYPE_NONE;
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+ girq->handler = handle_simple_irq;
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+
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+ rt_gpio_w32(rg, GPIO_REG_RENA, 0);
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+ rt_gpio_w32(rg, GPIO_REG_FENA, 0);
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+ }
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+
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+ return devm_gpiochip_add_data(dev, &rg->chip, rg);
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+}
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+
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+static const struct of_device_id ralink_gpio_match[] = {
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+ { .compatible = "ralink,rt2880-gpio" },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, ralink_gpio_match);
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+
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+static struct platform_driver ralink_gpio_driver = {
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+ .probe = ralink_gpio_probe,
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+ .driver = {
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+ .name = "ralink_gpio",
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+ .of_match_table = ralink_gpio_match,
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+ },
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+};
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+
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+static int __init ralink_gpio_init(void)
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+{
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+ return platform_driver_register(&ralink_gpio_driver);
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+}
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+
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+subsys_initcall(ralink_gpio_init);
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