// SPDX-License-Identifier: (GPL-2.0 OR MIT) /dts-v1/; #include #include #include #include "mt7986a.dtsi" / { model = "ASUS TUF-AX6000"; compatible = "asus,tuf-ax6000", "mediatek,mt7986a"; aliases { serial0 = &uart0; label-mac-device = &gmac0; led-boot = &led_system; led-failsafe = &led_system; led-running = &led_system; led-upgrade = &led_system; }; chosen { stdout-path = "serial0:115200n8"; bootargs-override = ""; }; memory { reg = <0 0x40000000 0 0x20000000>; }; keys { compatible = "gpio-keys"; reset { label = "reset"; gpios = <&pio 9 GPIO_ACTIVE_LOW>; linux,code = ; }; mesh { label = "wps"; gpios = <&pio 10 GPIO_ACTIVE_LOW>; linux,code = ; }; }; leds { compatible = "gpio-leds"; wlan { function = LED_FUNCTION_WLAN; color = ; gpios = <&pio 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy1tpt"; }; led_system: system { label = "white:system"; gpios = <&pio 11 GPIO_ACTIVE_HIGH>; }; wan-red { function = LED_FUNCTION_WAN; color = ; gpios = <&pio 12 GPIO_ACTIVE_LOW>; }; cover-blue { label = "blue:cover"; gpios = <&pio 20 GPIO_ACTIVE_HIGH>; }; cover-red { label = "red:cover"; gpios = <&pio 21 GPIO_ACTIVE_HIGH>; }; cover-green { label = "green:cover"; gpios = <&pio 22 GPIO_ACTIVE_HIGH>; }; }; reg_3p3v: regulator-3p3v { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; reg_5v: regulator-5v { compatible = "regulator-fixed"; regulator-name = "fixed-5V"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; regulator-always-on; }; }; &crypto { status = "okay"; }; ð { status = "okay"; gmac0: mac@0 { /* LAN */ compatible = "mediatek,eth-mac"; reg = <0>; nvmem-cells = <&macaddr_factory_4>; nvmem-cell-names = "mac-address"; phy-mode = "2500base-x"; fixed-link { speed = <2500>; full-duplex; pause; }; }; gmac1: mac@1 { /* WAN */ compatible = "mediatek,eth-mac"; reg = <1>; phy-mode = "2500base-x"; phy-handle = <&phy6>; }; mdio: mdio-bus { #address-cells = <1>; #size-cells = <0>; }; }; &mdio { reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; reset-delay-us = <50000>; reset-post-delay-us = <20000>; phy5: phy@5 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <5>; mxl,led-drive-vdd; mxl,led-config = <0x03f0 0x0 0x0 0x0>; }; phy6: phy@6 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <6>; /* LED0: CONN (WAN white) */ mxl,led-config = <0x03f0 0x0 0x0 0x0>; }; switch: switch@1f { compatible = "mediatek,mt7531"; reg = <31>; reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; reset-assert-us = <10000>; reset-deassert-us = <10000>; }; }; &pio { spi_flash_pins: spi-flash-pins-33-to-38 { mux { function = "spi"; groups = "spi0", "spi0_wp_hold"; }; conf-pu { pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; drive-strength = <8>; mediatek,pull-up-adv = <0>; /* bias-disable */ }; conf-pd { pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; drive-strength = <8>; mediatek,pull-down-adv = <0>; /* bias-disable */ }; }; wf_2g_5g_pins: wf_2g_5g-pins { mux { function = "wifi"; groups = "wf_2g", "wf_5g"; }; conf { pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", "WF1_TOP_CLK", "WF1_TOP_DATA"; drive-strength = <4>; }; }; wf_dbdc_pins: wf-dbdc-pins { mux { function = "wifi"; groups = "wf_dbdc"; }; conf { pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", "WF1_TOP_CLK", "WF1_TOP_DATA"; drive-strength = <4>; }; }; }; &pcie_phy { status = "okay"; }; &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi_flash_pins>; status = "okay"; spi_nand_flash: flash@0 { compatible = "spi-nand"; reg = <0>; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <20000000>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* * ASUS bootloader tries to replace the partitions defined in * Device Tree and by that also deletes all additional properties * needed for UBI and NVMEM-on-UBI. * Prevent this from happening by tricking the loader to delete and * replace a bait node instead. */ partitions: dummy { compatible = "u-boot-dummy-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { reg = <0x0 0x0>; label = "remove_me"; }; }; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; partition@0 { reg = <0x0 0x400000>; label = "bootloader"; read-only; }; partition@400000 { compatible = "linux,ubi"; reg = <0x400000 0xfc00000>; label = "UBI_DEV"; volumes { ubi_factory: ubi-volume-factory { volname = "Factory"; }; }; }; }; }; }; &ubi_factory { nvmem-layout { compatible = "fixed-layout"; #address-cells = <1>; #size-cells = <1>; eeprom_factory_0: eeprom@0 { reg = <0x0 0x1000>; }; macaddr_factory_4: macaddr@4 { reg = <0x4 0x6>; }; }; }; &switch { ports { #address-cells = <1>; #size-cells = <0>; port@1 { reg = <1>; label = "lan4"; phy-handle = <&swphy1>; }; port@2 { reg = <2>; label = "lan3"; phy-handle = <&swphy2>; }; port@3 { reg = <3>; label = "lan2"; phy-handle = <&swphy3>; }; port@4 { reg = <4>; label = "lan1"; phy-handle = <&swphy4>; }; port@5 { reg = <5>; label = "lan5"; phy-mode = "2500base-x"; phy-handle = <&phy5>; }; port@6 { reg = <6>; label = "cpu"; ethernet = <&gmac0>; phy-mode = "2500base-x"; fixed-link { speed = <2500>; full-duplex; pause; }; }; }; mdio { #address-cells = <1>; #size-cells = <0>; swphy1: phy@1 { reg = <1>; mediatek,led-config = < 0x21 0x8009 /* BASIC_CTRL */ 0x22 0x0c00 /* ON_DURATION */ 0x23 0x1400 /* BLINK_DURATION */ 0x24 0x8000 /* LED0_ON_CTRL */ 0x25 0x0000 /* LED0_BLINK_CTRL */ 0x26 0xc007 /* LED1_ON_CTRL */ 0x27 0x003f /* LED1_BLINK_CTRL */ >; }; swphy2: phy@2 { reg = <2>; mediatek,led-config = < 0x21 0x8009 /* BASIC_CTRL */ 0x22 0x0c00 /* ON_DURATION */ 0x23 0x1400 /* BLINK_DURATION */ 0x24 0x8000 /* LED0_ON_CTRL */ 0x25 0x0000 /* LED0_BLINK_CTRL */ 0x26 0xc007 /* LED1_ON_CTRL */ 0x27 0x003f /* LED1_BLINK_CTRL */ >; }; swphy3: phy@3 { reg = <3>; mediatek,led-config = < 0x21 0x8009 /* BASIC_CTRL */ 0x22 0x0c00 /* ON_DURATION */ 0x23 0x1400 /* BLINK_DURATION */ 0x24 0x8000 /* LED0_ON_CTRL */ 0x25 0x0000 /* LED0_BLINK_CTRL */ 0x26 0xc007 /* LED1_ON_CTRL */ 0x27 0x003f /* LED1_BLINK_CTRL */ >; }; swphy4: phy@4 { reg = <4>; mediatek,led-config = < 0x21 0x8009 /* BASIC_CTRL */ 0x22 0x0c00 /* ON_DURATION */ 0x23 0x1400 /* BLINK_DURATION */ 0x24 0x8000 /* LED0_ON_CTRL */ 0x25 0x0000 /* LED0_BLINK_CTRL */ 0x26 0xc007 /* LED1_ON_CTRL */ 0x27 0x003f /* LED1_BLINK_CTRL */ >; }; }; }; &watchdog { status = "okay"; }; &wifi { nvmem-cells = <&eeprom_factory_0>; nvmem-cell-names = "eeprom"; pinctrl-names = "default", "dbdc"; pinctrl-0 = <&wf_2g_5g_pins>; pinctrl-1 = <&wf_dbdc_pins>; status = "okay"; }; &trng { status = "okay"; }; &uart0 { status = "okay"; }; &ssusb { vusb33-supply = <®_3p3v>; vbus-supply = <®_5v>; status = "okay"; }; &usb_phy { status = "okay"; };