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realtek: timer: Remove CEVT_RTL9300 completely
As the timer has been fixed now, we can drop the CEVT_RTL9300 timer all together. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
This commit is contained in:
Olliver Schinagl
Sander Vanheule
parent
68e28cdc47
commit
f6ba61b929
@ -1,204 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <asm/time.h>
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#include <asm/idle.h>
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#include <linux/interrupt.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <mach-rtl83xx.h>
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/*
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* Timer registers
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* the RTL9300/9310 SoCs have 6 timers, each register block 0x10 apart
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*/
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#define RTL9300_TC_DATA 0x0
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#define RTL9300_TC_CNT 0x4
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#define RTL9300_TC_CTRL 0x8
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#define RTL9300_TC_CTRL_MODE BIT(24)
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#define RTL9300_TC_CTRL_EN BIT(28)
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#define RTL9300_TC_INT 0xc
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#define RTL9300_TC_INT_IP BIT(16)
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#define RTL9300_TC_INT_IE BIT(20)
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/* Timer modes */
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#define TIMER_MODE_REPEAT 1
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#define TIMER_MODE_ONCE 0
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/* Minimum divider is 2 */
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#define DIVISOR_RTL9300 2
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#define N_BITS 28
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#define RTL9300_CLOCK_RATE 87500000
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struct rtl9300_clk_dev {
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struct clock_event_device clkdev;
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void __iomem *base;
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};
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static void __iomem *rtl9300_tc_base(struct clock_event_device *clk)
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{
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struct rtl9300_clk_dev *rtl_clk = container_of(clk, struct rtl9300_clk_dev, clkdev);
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return rtl_clk->base;
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}
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static irqreturn_t rtl9300_timer_interrupt(int irq, void *dev_id)
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{
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struct rtl9300_clk_dev *rtl_clk = dev_id;
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struct clock_event_device *clk = &rtl_clk->clkdev;
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u32 v = readl(rtl_clk->base + RTL9300_TC_INT);
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/* Acknowledge the IRQ */
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v |= RTL9300_TC_INT_IP;
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writel(v, rtl_clk->base + RTL9300_TC_INT);
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clk->event_handler(clk);
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return IRQ_HANDLED;
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}
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static void rtl9300_clock_stop(void __iomem *base)
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{
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u32 v;
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writel(0, base + RTL9300_TC_CTRL);
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/* Acknowledge possibly pending IRQ */
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v = readl(base + RTL9300_TC_INT);
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writel(v | RTL9300_TC_INT_IP, base + RTL9300_TC_INT);
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}
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static void rtl9300_timer_start(void __iomem *base, bool periodic)
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{
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u32 v = (periodic ? RTL9300_TC_CTRL_MODE : 0) | RTL9300_TC_CTRL_EN | DIVISOR_RTL9300;
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writel(0, base + RTL9300_TC_CNT);
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pr_debug("------------- starting timer base %08x\n", (u32)base);
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writel(v, base + RTL9300_TC_CTRL);
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}
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static int rtl9300_next_event(unsigned long delta, struct clock_event_device *clk)
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{
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void __iomem *base = rtl9300_tc_base(clk);
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rtl9300_clock_stop(base);
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writel(delta, base + RTL9300_TC_DATA);
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rtl9300_timer_start(base, TIMER_MODE_ONCE);
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return 0;
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}
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static int rtl9300_state_periodic(struct clock_event_device *clk)
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{
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void __iomem *base = rtl9300_tc_base(clk);
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pr_debug("------------- rtl9300_state_periodic %08x\n", (u32)base);
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rtl9300_clock_stop(base);
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writel(RTL9300_CLOCK_RATE / HZ, base + RTL9300_TC_DATA);
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rtl9300_timer_start(base, TIMER_MODE_REPEAT);
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return 0;
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}
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static int rtl9300_state_oneshot(struct clock_event_device *clk)
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{
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void __iomem *base = rtl9300_tc_base(clk);
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pr_debug("------------- rtl9300_state_oneshot %08x\n", (u32)base);
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rtl9300_clock_stop(base);
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writel(RTL9300_CLOCK_RATE / HZ, base + RTL9300_TC_DATA);
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rtl9300_timer_start(base, TIMER_MODE_ONCE);
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return 0;
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}
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static int rtl9300_shutdown(struct clock_event_device *clk)
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{
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void __iomem *base = rtl9300_tc_base(clk);
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pr_debug("------------- rtl9300_shutdown %08x\n", (u32)base);
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rtl9300_clock_stop(base);
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return 0;
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}
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static void rtl9300_clock_setup(void __iomem *base)
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{
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u32 v;
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/* Disable timer */
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writel(0, base + RTL9300_TC_CTRL);
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/* Acknowledge possibly pending IRQ */
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v = readl(base + RTL9300_TC_INT);
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writel(v | RTL9300_TC_INT_IP, base + RTL9300_TC_INT);
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/* Setup maximum period (for use as clock-source) */
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writel(0x0fffffff, base + RTL9300_TC_DATA);
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}
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static DEFINE_PER_CPU(struct rtl9300_clk_dev, rtl9300_clockevent);
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static DEFINE_PER_CPU(char [18], rtl9300_clock_name);
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void rtl9300_clockevent_init(void)
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{
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int cpu = smp_processor_id();
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int irq;
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struct rtl9300_clk_dev *rtl_clk = &per_cpu(rtl9300_clockevent, cpu);
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struct clock_event_device *cd = &rtl_clk->clkdev;
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unsigned char *name = per_cpu(rtl9300_clock_name, cpu);
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unsigned long flags = IRQF_PERCPU | IRQF_TIMER;
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struct device_node *node;
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pr_info("%s called for cpu%d\n", __func__, cpu);
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BUG_ON(cpu > 3); /* Only have 4 general purpose timers */
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node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300clock");
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if (!node) {
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pr_err("No DT entry found for realtek,rtl9300clock\n");
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return;
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}
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irq = irq_of_parse_and_map(node, cpu);
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pr_info("%s using IRQ %d\n", __func__, irq);
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rtl_clk->base = of_iomap(node, cpu);
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if (!rtl_clk->base) {
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pr_err("cannot map timer for cpu %d", cpu);
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return;
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}
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rtl9300_clock_setup(rtl_clk->base);
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sprintf(name, "rtl9300-counter-%d", cpu);
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cd->name = name;
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cd->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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clockevent_set_clock(cd, RTL9300_CLOCK_RATE);
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cd->max_delta_ns = clockevent_delta2ns(0x0fffffff, cd);
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cd->max_delta_ticks = 0x0fffffff;
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cd->min_delta_ns = clockevent_delta2ns(0x20, cd);
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cd->min_delta_ticks = 0x20;
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cd->rating = 300;
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cd->irq = irq;
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cd->cpumask = cpumask_of(cpu);
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cd->set_next_event = rtl9300_next_event;
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cd->set_state_shutdown = rtl9300_shutdown;
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cd->set_state_periodic = rtl9300_state_periodic;
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cd->set_state_oneshot = rtl9300_state_oneshot;
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clockevents_register_device(cd);
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irq_set_affinity(irq, cd->cpumask);
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if (request_irq(irq, rtl9300_timer_interrupt, flags, name, rtl_clk))
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pr_err("Failed to request irq %d (%s)\n", irq, name);
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writel(RTL9300_TC_INT_IE, rtl_clk->base + RTL9300_TC_INT);
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}
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@ -84,13 +84,3 @@ Submitted-by: Birger Koblitz <git@birger-koblitz.de>
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source "arch/mips/alchemy/Kconfig"
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source "arch/mips/ath25/Kconfig"
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source "arch/mips/ath79/Kconfig"
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@@ -1112,6 +1162,9 @@ config CEVT_GT641XX
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config CEVT_R4K
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bool
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+config CEVT_RTL9300
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+ bool
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+
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config CEVT_SB1250
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bool
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@ -1,54 +0,0 @@
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From 775d903216a08c2a8009863d2f9c33f62657ba94 Mon Sep 17 00:00:00 2001
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From: Birger Koblitz <git@birger-koblitz.de>
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Date: Thu, 6 Jan 2022 20:27:01 +0100
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Subject: [PATCH] realtek: Replace the RTL9300 generic timer with a CEVT timer
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The RTL9300 has a broken R4K MIPS timer interrupt, however, the
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R4K clocksource works. We replace the RTL9300 timer with a
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Clock Event Timer (CEVT), which is VSMP aware and can be instantiated
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as part of brining a VSMTP cpu up instead of the R4K CEVT source.
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For this we place the RTL9300 CEVT timer in arch/mips/kernel
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together with other MIPS CEVT timers, initialize the SoC IRQs
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from a modified smp-mt.c and instantiate each timer as part
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of the MIPS time setup in arch/mips/include/asm/time.h instead
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of the R4K CEVT, similarly as is done by other MIPS CEVT timers.
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Submitted-by: Birger Koblitz <git@birger-koblitz.de>
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---
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arch/mips/kernel/Makefile | 1 +
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arch/mips/include/asm/time.h | 7 +++++++
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2 files changed, 8 insertions(+)
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--- a/arch/mips/kernel/Makefile
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+++ b/arch/mips/kernel/Makefile
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@@ -27,6 +27,7 @@ obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm14
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obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
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obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o
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obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
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+obj-$(CONFIG_CEVT_RTL9300) += cevt-rtl9300.o
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obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
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obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
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obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
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--- a/arch/mips/include/asm/time.h
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+++ b/arch/mips/include/asm/time.h
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@@ -15,6 +15,8 @@
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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+extern void rtl9300_clockevent_init(void);
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+
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extern spinlock_t rtc_lock;
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/*
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@@ -43,6 +45,11 @@ extern int r4k_clockevent_init(void);
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static inline int mips_clockevent_init(void)
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{
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+#ifdef CONFIG_CEVT_RTL9300
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+ rtl9300_clockevent_init();
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+ return 0;
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+#endif
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+
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#ifdef CONFIG_CEVT_R4K
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return r4k_clockevent_init();
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#else
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