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x86: copy 5.15 patches to 6.1
Copy existing patches from 5.15 to 6.1 Signed-off-by: Pascal Coudurier <coudu@gmx.com>
This commit is contained in:
Pascal Coudurier
Christian Marangi
parent
6bf8193b25
commit
f23015b18e
13
target/linux/x86/patches-6.1/100-fix_cs5535_clockevt.patch
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13
target/linux/x86/patches-6.1/100-fix_cs5535_clockevt.patch
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@ -0,0 +1,13 @@
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--- a/drivers/clocksource/timer-cs5535.c
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+++ b/drivers/clocksource/timer-cs5535.c
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@@ -127,7 +127,9 @@ static irqreturn_t mfgpt_tick(int irq, v
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cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP,
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MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
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- cs5535_clockevent.event_handler(&cs5535_clockevent);
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+ if (cs5535_clockevent.event_handler)
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+ cs5535_clockevent.event_handler(&cs5535_clockevent);
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+
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return IRQ_HANDLED;
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}
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280
target/linux/x86/patches-6.1/103-pcengines_apu6_platform.patch
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280
target/linux/x86/patches-6.1/103-pcengines_apu6_platform.patch
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@ -0,0 +1,280 @@
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From 970d9af9015a387bb81841faf05dcc1a171eb97a Mon Sep 17 00:00:00 2001
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From: Philip Prindeville <philipp@redfish-solutions.com>
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Date: Sun, 1 Jan 2023 15:25:04 -0700
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Subject: [PATCH v3 1/1] x86: Support APU5 in PCEngines platform driver
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To: platform-driver-x86@vger.kernel.org, linux-x86_64@vger.kernel.org
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Cc: Ed Wildgoose <lists@wildgooses.com>, Andres Salomon <dilinger@queued.net>, Andreas Eberlein <foodeas@aeberlein.de>, Paul Spooren <paul@spooren.de>
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PCEngines make a number of SBC. APU5 has 5 mpcie slots + MSATA.
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It also has support for 3x LTE modems with 6x SIM slots (pairs with a
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SIM switch device). Each mpcie slot for modems has a reset GPIO
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To ensure that the naming is sane between APU2-6 the GPIOS are
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renamed to be modem1-reset, modem2-reset, etc. This is significant
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because the slots that can be reset change between APU2 and APU3/4
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GPIO for simswap is moved to the end of the list as it could be dropped
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for APU2 boards (but causes no harm to leave it in, hardware could be
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added to a future rev of the board).
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Structure of the GPIOs for APU5 is extremely similar to APU2-4, but
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many lines are moved around and there are simply more
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modems/resets/sim-swap lines to breakout.
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Also added APU6, which is essentially APU4 with a different ethernet
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interface and SFP cage on eth0.
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Revision history:
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v1: originally titled, "apu6: add apu6 variation to apu2 driver family"
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this dealt only with detecting the APUv6, which is otherwise identical
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to the v4 excepting the SFP cage on eth0.
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v2: at Ed's request, merged with his previous pull-request titled
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"x86: Support APU5 in PCEngines platform driver", and some cleanup
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to that changeset (including dropping the table "apu5_driver_data"
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which did not have a defined type "struct apu_driver_data"), but got
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mistitled when the Subject of that commit got accidentally dropped.
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v3: retitled to match Ed's previous pull-request.
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Cc: platform-driver-x86@vger.kernel.org
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Cc: linux-x86_64@vger.kernel.org
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Reviewed-by: Andreas Eberlein <foodeas@aeberlein.de>
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Reviewed-by: Paul Spooren <paul@spooren.de>
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Signed-off-by: Ed Wildgoose <lists@wildgooses.com>
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Sighed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
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---
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drivers/leds/leds-apu.c | 2 +-
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drivers/platform/x86/Kconfig | 4 +-
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drivers/platform/x86/pcengines-apuv2.c | 118 ++++++++++++++++++++++---
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3 files changed, 107 insertions(+), 17 deletions(-)
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--- a/drivers/leds/leds-apu.c
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+++ b/drivers/leds/leds-apu.c
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@@ -183,7 +183,7 @@ static int __init apu_led_init(void)
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if (!(dmi_match(DMI_SYS_VENDOR, "PC Engines") &&
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(dmi_match(DMI_PRODUCT_NAME, "APU") || dmi_match(DMI_PRODUCT_NAME, "apu1")))) {
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- pr_err("No PC Engines APUv1 board detected. For APUv2,3 support, enable CONFIG_PCENGINES_APU2\n");
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+ pr_err("No PC Engines APUv1 board detected. For APUv2,3,4,5,6 support, enable CONFIG_PCENGINES_APU2\n");
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return -ENODEV;
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}
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--- a/drivers/platform/x86/Kconfig
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+++ b/drivers/platform/x86/Kconfig
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@@ -661,7 +661,7 @@ config XO1_RFKILL
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laptop.
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config PCENGINES_APU2
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- tristate "PC Engines APUv2/3 front button and LEDs driver"
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+ tristate "PC Engines APUv2/3/4/5/6 front button and LEDs driver"
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depends on INPUT && INPUT_KEYBOARD && GPIOLIB
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depends on LEDS_CLASS
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select GPIO_AMD_FCH
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@@ -669,7 +669,7 @@ config PCENGINES_APU2
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select LEDS_GPIO
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help
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This driver provides support for the front button and LEDs on
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- PC Engines APUv2/APUv3 board.
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+ PC Engines APUv2/APUv3/APUv4/APUv5/APUv6 board.
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To compile this driver as a module, choose M here: the module
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will be called pcengines-apuv2.
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--- a/drivers/platform/x86/pcengines-apuv2.c
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+++ b/drivers/platform/x86/pcengines-apuv2.c
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@@ -1,10 +1,12 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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- * PC-Engines APUv2/APUv3 board platform driver
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+ * PC-Engines APUv2-6 board platform driver
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* for GPIO buttons and LEDs
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*
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* Copyright (C) 2018 metux IT consult
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+ * Copyright (C) 2022 Ed Wildgoose <lists@wildgooses.com>
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+ * Copyright (C) 2022 Philip Prindeville <philipp@redfish-solutions.com>
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* Author: Enrico Weigelt <info@metux.net>
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*/
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@@ -22,38 +24,70 @@
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#include <linux/platform_data/gpio/gpio-amd-fch.h>
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/*
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- * NOTE: this driver only supports APUv2/3 - not APUv1, as this one
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+ * NOTE: this driver only supports APUv2-6 - not APUv1, as this one
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* has completely different register layouts.
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*/
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+/*
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+ * There are a number of APU variants, with differing features
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+ * APU2 has SIM slots 1/2 mapping to mPCIe sockets 1/2
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+ * APU3/4 moved SIM slot 1 to mPCIe socket 3, ie logically reversed
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+ * However, most APU3/4 have a SIM switch which we default on to reverse
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+ * the order and keep physical SIM order matching physical modem order
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+ * APU6 is approximately the same as APU4 with different ethernet layout
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+ *
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+ * APU5 has 3x SIM sockets, all with a SIM switch
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+ * several GPIOs are shuffled (see schematic), including MODESW
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+ */
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+
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/* Register mappings */
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#define APU2_GPIO_REG_LED1 AMD_FCH_GPIO_REG_GPIO57
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#define APU2_GPIO_REG_LED2 AMD_FCH_GPIO_REG_GPIO58
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#define APU2_GPIO_REG_LED3 AMD_FCH_GPIO_REG_GPIO59_DEVSLP1
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#define APU2_GPIO_REG_MODESW AMD_FCH_GPIO_REG_GPIO32_GE1
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#define APU2_GPIO_REG_SIMSWAP AMD_FCH_GPIO_REG_GPIO33_GE2
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-#define APU2_GPIO_REG_MPCIE2 AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
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-#define APU2_GPIO_REG_MPCIE3 AMD_FCH_GPIO_REG_GPIO51
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+#define APU2_GPIO_REG_RESETM1 AMD_FCH_GPIO_REG_GPIO51
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+#define APU2_GPIO_REG_RESETM2 AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
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+
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+#define APU5_GPIO_REG_MODESW AMT_FCH_GPIO_REG_GEVT22
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+#define APU5_GPIO_REG_SIMSWAP1 AMD_FCH_GPIO_REG_GPIO68
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+#define APU5_GPIO_REG_SIMSWAP2 AMD_FCH_GPIO_REG_GPIO32_GE1
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+#define APU5_GPIO_REG_SIMSWAP3 AMD_FCH_GPIO_REG_GPIO33_GE2
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+#define APU5_GPIO_REG_RESETM1 AMD_FCH_GPIO_REG_GPIO51
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+#define APU5_GPIO_REG_RESETM2 AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
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+#define APU5_GPIO_REG_RESETM3 AMD_FCH_GPIO_REG_GPIO64
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/* Order in which the GPIO lines are defined in the register list */
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#define APU2_GPIO_LINE_LED1 0
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#define APU2_GPIO_LINE_LED2 1
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#define APU2_GPIO_LINE_LED3 2
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#define APU2_GPIO_LINE_MODESW 3
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-#define APU2_GPIO_LINE_SIMSWAP 4
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-#define APU2_GPIO_LINE_MPCIE2 5
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-#define APU2_GPIO_LINE_MPCIE3 6
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+#define APU2_GPIO_LINE_RESETM1 4
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+#define APU2_GPIO_LINE_RESETM2 5
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+#define APU2_GPIO_LINE_SIMSWAP 6
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+
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+#define APU5_GPIO_LINE_LED1 0
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+#define APU5_GPIO_LINE_LED2 1
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+#define APU5_GPIO_LINE_LED3 2
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+#define APU5_GPIO_LINE_MODESW 3
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+#define APU5_GPIO_LINE_RESETM1 4
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+#define APU5_GPIO_LINE_RESETM2 5
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+#define APU5_GPIO_LINE_RESETM3 6
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+#define APU5_GPIO_LINE_SIMSWAP1 7
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+#define APU5_GPIO_LINE_SIMSWAP2 8
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+#define APU5_GPIO_LINE_SIMSWAP3 9
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+
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-/* GPIO device */
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+/* GPIO device - APU2/3/4/6 */
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static int apu2_gpio_regs[] = {
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[APU2_GPIO_LINE_LED1] = APU2_GPIO_REG_LED1,
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[APU2_GPIO_LINE_LED2] = APU2_GPIO_REG_LED2,
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[APU2_GPIO_LINE_LED3] = APU2_GPIO_REG_LED3,
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[APU2_GPIO_LINE_MODESW] = APU2_GPIO_REG_MODESW,
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+ [APU2_GPIO_LINE_RESETM1] = APU2_GPIO_REG_RESETM1,
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+ [APU2_GPIO_LINE_RESETM2] = APU2_GPIO_REG_RESETM2,
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[APU2_GPIO_LINE_SIMSWAP] = APU2_GPIO_REG_SIMSWAP,
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- [APU2_GPIO_LINE_MPCIE2] = APU2_GPIO_REG_MPCIE2,
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- [APU2_GPIO_LINE_MPCIE3] = APU2_GPIO_REG_MPCIE3,
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};
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static const char * const apu2_gpio_names[] = {
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@@ -61,9 +95,9 @@ static const char * const apu2_gpio_name
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[APU2_GPIO_LINE_LED2] = "front-led2",
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[APU2_GPIO_LINE_LED3] = "front-led3",
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[APU2_GPIO_LINE_MODESW] = "front-button",
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+ [APU2_GPIO_LINE_RESETM1] = "modem1-reset",
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+ [APU2_GPIO_LINE_RESETM2] = "modem2-reset",
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[APU2_GPIO_LINE_SIMSWAP] = "simswap",
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- [APU2_GPIO_LINE_MPCIE2] = "mpcie2_reset",
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- [APU2_GPIO_LINE_MPCIE3] = "mpcie3_reset",
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};
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static const struct amd_fch_gpio_pdata board_apu2 = {
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@@ -72,6 +106,40 @@ static const struct amd_fch_gpio_pdata b
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.gpio_names = apu2_gpio_names,
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};
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+/* GPIO device - APU5 */
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+
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+static int apu5_gpio_regs[] = {
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+ [APU5_GPIO_LINE_LED1] = APU2_GPIO_REG_LED1,
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+ [APU5_GPIO_LINE_LED2] = APU2_GPIO_REG_LED2,
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+ [APU5_GPIO_LINE_LED3] = APU2_GPIO_REG_LED3,
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+ [APU5_GPIO_LINE_MODESW] = APU5_GPIO_REG_MODESW,
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+ [APU5_GPIO_LINE_RESETM1] = APU5_GPIO_REG_RESETM1,
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+ [APU5_GPIO_LINE_RESETM2] = APU5_GPIO_REG_RESETM2,
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+ [APU5_GPIO_LINE_RESETM3] = APU5_GPIO_REG_RESETM3,
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+ [APU5_GPIO_LINE_SIMSWAP1] = APU5_GPIO_REG_SIMSWAP1,
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+ [APU5_GPIO_LINE_SIMSWAP2] = APU5_GPIO_REG_SIMSWAP2,
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+ [APU5_GPIO_LINE_SIMSWAP3] = APU5_GPIO_REG_SIMSWAP3,
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+};
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+
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+static const char * const apu5_gpio_names[] = {
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+ [APU5_GPIO_LINE_LED1] = "front-led1",
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+ [APU5_GPIO_LINE_LED2] = "front-led2",
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+ [APU5_GPIO_LINE_LED3] = "front-led3",
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+ [APU5_GPIO_LINE_MODESW] = "front-button",
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+ [APU5_GPIO_LINE_RESETM1] = "modem1-reset",
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+ [APU5_GPIO_LINE_RESETM2] = "modem2-reset",
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+ [APU5_GPIO_LINE_RESETM3] = "modem3-reset",
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+ [APU5_GPIO_LINE_SIMSWAP1] = "simswap1",
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+ [APU5_GPIO_LINE_SIMSWAP2] = "simswap2",
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+ [APU5_GPIO_LINE_SIMSWAP3] = "simswap3",
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+};
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+
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+static const struct amd_fch_gpio_pdata board_apu5 = {
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+ .gpio_num = ARRAY_SIZE(apu5_gpio_regs),
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+ .gpio_reg = apu5_gpio_regs,
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+ .gpio_names = apu5_gpio_names,
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+};
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+
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/* GPIO LEDs device */
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static const struct gpio_led apu2_leds[] = {
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@@ -215,6 +283,24 @@ static const struct dmi_system_id apu_gp
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},
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.driver_data = (void *)&board_apu2,
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},
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+ /* APU5 w/ mainline BIOS */
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+ {
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+ .ident = "apu5",
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+ .matches = {
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+ DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
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+ DMI_MATCH(DMI_BOARD_NAME, "apu5")
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+ },
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+ .driver_data = (void *)&board_apu5,
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+ },
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+ /* APU6 w/ mainline BIOS */
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+ {
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+ .ident = "apu6",
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+ .matches = {
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+ DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
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+ DMI_MATCH(DMI_BOARD_NAME, "apu6")
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+ },
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+ .driver_data = (void *)&board_apu2,
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+ },
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{}
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};
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@@ -249,7 +335,7 @@ static int __init apu_board_init(void)
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id = dmi_first_match(apu_gpio_dmi_table);
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if (!id) {
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- pr_err("failed to detect APU board via DMI\n");
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+ pr_err("No APU board detected via DMI\n");
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return -ENODEV;
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}
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@@ -288,8 +374,12 @@ module_init(apu_board_init);
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module_exit(apu_board_exit);
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MODULE_AUTHOR("Enrico Weigelt, metux IT consult <info@metux.net>");
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-MODULE_DESCRIPTION("PC Engines APUv2/APUv3 board GPIO/LEDs/keys driver");
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+MODULE_DESCRIPTION("PC Engines APUv2-6 board GPIO/LEDs/keys driver");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(dmi, apu_gpio_dmi_table);
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MODULE_ALIAS("platform:pcengines-apuv2");
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+MODULE_ALIAS("platform:pcengines-apuv3");
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+MODULE_ALIAS("platform:pcengines-apuv4");
|
||||||
|
+MODULE_ALIAS("platform:pcengines-apuv5");
|
||||||
|
+MODULE_ALIAS("platform:pcengines-apuv6");
|
||||||
|
MODULE_SOFTDEP("pre: platform:" AMD_FCH_GPIO_DRIVER_NAME " platform:leds-gpio platform:gpio_keys_polled");
|
||||||
@ -0,0 +1,52 @@
|
|||||||
|
From: Hans de Goede <hdegoede@redhat.com>
|
||||||
|
Date: Thu, 28 Jul 2022 20:06:35 +0200
|
||||||
|
Subject: platform/x86: pmc_atom: Match all Lex BayTrail boards with
|
||||||
|
critclk_systems DMI table
|
||||||
|
|
||||||
|
The critclk_systems[] DMI match table already contains 2 Lex BayTrail
|
||||||
|
boards and patches were just submitted to add 3 more entries for the
|
||||||
|
following models: 3I380NX, 3I380A, 3I380CW.
|
||||||
|
|
||||||
|
Looking at: https://www.lex.com.tw/products/embedded-ipc-board/
|
||||||
|
we can see that Lex BayTrail makes many embedded boards with
|
||||||
|
multiple ethernet boards and none of their products are battery
|
||||||
|
powered so we don't need to worry (too much) about power consumption
|
||||||
|
when suspended.
|
||||||
|
|
||||||
|
Add a new DMI match which simply matches all Lex BayTrail boards and drop
|
||||||
|
the 2 existing board specific quirks.
|
||||||
|
|
||||||
|
Reported-by: Michael Schöne <michael.schoene@rhebo.com>
|
||||||
|
Reported-by: Paul Spooren <paul.spooren@rhebo.com>
|
||||||
|
Reported-by: Matwey V. Kornilov <matwey@sai.msu.ru>
|
||||||
|
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
|
||||||
|
---
|
||||||
|
--- a/drivers/platform/x86/pmc_atom.c
|
||||||
|
+++ b/drivers/platform/x86/pmc_atom.c
|
||||||
|
@@ -376,19 +376,15 @@ static const struct dmi_system_id critcl
|
||||||
|
},
|
||||||
|
},
|
||||||
|
{
|
||||||
|
- /* pmc_plt_clk0 - 3 are used for the 4 ethernet controllers */
|
||||||
|
- .ident = "Lex 3I380D",
|
||||||
|
+ /*
|
||||||
|
+ * Lex System / Lex Computech Co. makes a lot of Bay Trail
|
||||||
|
+ * based embedded boards which often come with multiple
|
||||||
|
+ * ethernet controllers using multiple pmc_plt_clks. See:
|
||||||
|
+ * https://www.lex.com.tw/products/embedded-ipc-board/
|
||||||
|
+ */
|
||||||
|
+ .ident = "Lex BayTrail",
|
||||||
|
.matches = {
|
||||||
|
DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"),
|
||||||
|
- DMI_MATCH(DMI_PRODUCT_NAME, "3I380D"),
|
||||||
|
- },
|
||||||
|
- },
|
||||||
|
- {
|
||||||
|
- /* pmc_plt_clk* - are used for ethernet controllers */
|
||||||
|
- .ident = "Lex 2I385SW",
|
||||||
|
- .matches = {
|
||||||
|
- DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"),
|
||||||
|
- DMI_MATCH(DMI_PRODUCT_NAME, "2I385SW"),
|
||||||
|
},
|
||||||
|
},
|
||||||
|
{
|
||||||
Loading…
Reference in New Issue
Block a user