RepoMirrors/openwrt
1
0
Fork 0
mirror of git://git.openwrt.org/openwrt/openwrt.git synced 2024-12-17 12:24:33 +00:00
Code Issues Packages Projects Releases Wiki Activity

ramips: fix some clocks in mt7621.dtsi

Browse Source 
As the cpu clock calculation has been fixed, the clock for gic and spi
should be also fixed.

Signed-off-by: Weijie Gao <hackpascal@gmail.com>
This commit is contained in:
Weijie Gao 2018-11-19 00:07:01 +08:00 committed by John Crispin
parent c7ca224299
commit ed25e3ac02
1 changed files with 2 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
target/linux/ramips/dts/mt7621.dtsi
View File

@ -41,14 +41,6 @@
clock-output-names = "cpu", "bus"; clock-output-names = "cpu", "bus";
}; };
cpuclock: cpuclock {
#clock-cells = <0>;
compatible = "fixed-clock";
/* FIXME: there should be way to detect this */
clock-frequency = <880000000>;
};
sysclock: sysclock { sysclock: sysclock {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
@ -176,7 +168,6 @@
compatible = "ns16550a"; compatible = "ns16550a";
reg = <0xc00 0x100>; reg = <0xc00 0x100>;
clocks = <&sysclock>;
clock-frequency = <50000000>; clock-frequency = <50000000>;
interrupt-parent = <&gic>; interrupt-parent = <&gic>;
@ -193,7 +184,7 @@
compatible = "ralink,mt7621-spi"; compatible = "ralink,mt7621-spi";
reg = <0xb00 0x100>; reg = <0xb00 0x100>;
clocks = <&sysclock>; clocks = <&pll MT7621_CLK_BUS>;
resets = <&rstctrl 18>; resets = <&rstctrl 18>;
reset-names = "spi"; reset-names = "spi";
@ -402,7 +393,7 @@
timer { timer {
compatible = "mti,gic-timer"; compatible = "mti,gic-timer";
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
clocks = <&cpuclock>; clocks = <&pll MT7621_CLK_CPU>;
}; };
}; };