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ath79: reduce spi-max-frequency to 50 MHz
The introduction ofebf0d8dade
("ath79: add new ar934x spi driver") made the SPI memory unusable on devices with very high spi-max-frequency (104 MHz). Here's how the actual clock is calculated: (AHB_CLK/((CLOCK_DIVIDER+1)*2)) where AHB_CLK is a fixed clock (e.g. 200MHz on AR9331) and CLOCK_DIVIDER is the parameter we can set. Highest clock according to this formula is AHB_CLK/2 (100MHz, but that didn't work in device tests). The next possible value is AHB_CLK/4 (50MHz). Speeds between 50 MHz and 100 MHz will be rounded down, so using values higher than 50 MHz does not provide any benefit. Consequently, this patch reduces spi-max-frequency for all devices with values higher than 50 MHz to 50 MHz (effectively, this only affects devices with 104 MHz before this patch). Tested on GL.inet GL-AR150: Boot fails with 104 MHz but is successful with both 50 MHz and 80 MHz (fast-read), where the latter two yield identical read speeds. Fixes:ebf0d8dade
("ath79: add new ar934x spi driver") Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
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ebc090e420
@ -86,7 +86,7 @@
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flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <104000000>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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partitions {
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@ -75,7 +75,7 @@
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flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <104000000>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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partitions {
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@ -73,7 +73,7 @@
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flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <104000000>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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partitions {
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@ -68,7 +68,7 @@
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flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <104000000>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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partitions {
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@ -120,7 +120,7 @@
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/* Spansion S25FL032PIF SPI flash */
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flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <104000000>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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partitions {
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@ -114,7 +114,7 @@
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flash@0 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <104000000>;
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spi-max-frequency = <50000000>;
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reg = <0>;
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partitions {
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