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add interrupt debugging; fix bug with the AP60 interrupt handler
SVN-Revision: 3250
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5dc49bf217
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@ -92,11 +92,12 @@ diff -Nur linux-2.6.15/arch/mips/aruba/idtIRQ.S linux-2.6.15-openwrt/arch/mips/a
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diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/aruba/irq.c
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--- linux-2.6.15/arch/mips/aruba/irq.c 1970-01-01 01:00:00.000000000 +0100
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+++ linux-2.6.15-openwrt/arch/mips/aruba/irq.c 2006-01-10 00:32:32.000000000 +0100
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@@ -0,0 +1,424 @@
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@@ -0,0 +1,447 @@
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+/**************************************************************************
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+ *
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+ * BRIEF MODULE DESCRIPTION
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+ * Interrupt routines for IDT EB434 boards
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+ * Interrupt routines for IDT EB434 boards / Atheros boards
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+ * Modified by Aruba Networks
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+ *
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+ * Copyright 2004 IDT Inc. (rischelp@idt.com)
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+ *
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@ -275,7 +276,6 @@ diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/arub
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ addr = intr_group_muscat[group].base_addr;
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+ // unmask intr within group
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+ WRITE_MASK_MUSCAT(addr, READ_MASK_MUSCAT(addr) & ~intr_bit);
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+ break;
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+ case MACH_ARUBA_AP65:
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@ -342,7 +342,7 @@ diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/arub
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+ mask = READ_MASK_MERLOT(addr);
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+ mask &= ~intr_bit;
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+ WRITE_MASK_MERLOT(addr, mask);
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+ if (!mask)
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+ if (READ_MASK_MERLOT(addr))
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+ disable_local_irq(group_to_ip(group));
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+ break;
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+ }
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@ -381,11 +381,9 @@ diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/arub
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+
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+ local_irq_save(flags);
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+ if (irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)) {
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+ printk("warning: end_irq %d did not enable (%x) (ignoring)\n",
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+ printk("warning: end_irq %d did not enable (%x)\n",
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+ irq_nr, irq_desc[irq_nr].status);
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+ }
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+
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+ if (ip<0) {
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+ } else if (ip<0) {
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+ enable_local_irq(irq_nr);
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+ } else {
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+
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@ -474,6 +472,25 @@ diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/arub
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+{
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+ unsigned int pend, group, ip;
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+ volatile unsigned int *addr;
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+
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+ if(cp0_cause == 0) {
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+ printk("INTERRUPT(S) FIRED WHILE MASKED\n");
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+
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+ // debuging use -- figure out which interrupt(s) fired
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+ cp0_cause = read_c0_cause() & CAUSEF_IP;
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+ while (cp0_cause) {
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+ unsigned long intr_bit;
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+ unsigned int irq_nr;
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+ intr_bit = (31 - rc32434_clz(cp0_cause));
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+ irq_nr = intr_bit - GROUP0_IRQ_BASE;
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+ printk(" ---> MASKED IRQ %d\n",irq_nr);
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+ cp0_cause &= ~(1 << intr_bit);
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+ }
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+
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+ return;
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+ }
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+
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+
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+ switch (mips_machtype) {
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+ case MACH_ARUBA_AP70:
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+ if ((ip = (cp0_cause & 0x7c00))) {
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@ -490,7 +507,7 @@ diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/arub
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+ case MACH_ARUBA_AP65:
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+ case MACH_ARUBA_AP60:
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+ default:
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+ if (cp0_cause & 0x4000) {
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+ if (cp0_cause & 0x4000) { // 1 << (8 +6) == irq 6
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+ // Misc Interrupt
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+ group = 0;
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+ addr = intr_group_merlot[group].base_addr;
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@ -498,20 +515,26 @@ diff -Nur linux-2.6.15/arch/mips/aruba/irq.c linux-2.6.15-openwrt/arch/mips/arub
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+ pend &= READ_MASK_MERLOT(addr); // only unmasked interrupts
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+ /* handle one misc interrupt at a time */
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+ while (pend) {
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+ unsigned int intr_bit, irq_nr;
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+ intr_bit = pend ^ (pend - 1);
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+ irq_nr = ((31 - rc32434_clz(pend)) + GROUP0_IRQ_BASE);
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+ unsigned long intr_bit;
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+ unsigned int irq_nr;
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+
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+ intr_bit = (31 - rc32434_clz(pend));
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+ irq_nr = intr_bit + GROUP0_IRQ_BASE;
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+
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+ do_IRQ(irq_nr, regs);
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+ pend &= ~intr_bit;
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+ pend &= ~(1 << intr_bit);
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+ }
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+ }
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+ if (cp0_cause & 0x3c00) {
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+ if (cp0_cause & 0x3c00) { // irq 2-5
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+ while (cp0_cause) {
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+ unsigned int intr_bit, irq_nr;
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+ intr_bit = cp0_cause ^ (cp0_cause - 1);
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+ irq_nr = ((31 - rc32434_clz(cp0_cause)) - GROUP0_IRQ_BASE);
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+ unsigned long intr_bit;
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+ unsigned int irq_nr;
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+
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+ intr_bit = (31 - rc32434_clz(cp0_cause));
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+ irq_nr = intr_bit - GROUP0_IRQ_BASE;
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+
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+ do_IRQ(irq_nr, regs);
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+ cp0_cause &= ~intr_bit;
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+ cp0_cause &= ~(1 << intr_bit);
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+ }
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+ }
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+ break;
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