bcm53xx: update Disable MMU and Dcache during decompression
This replaces the old patch with the version from Florian. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 46504
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Hauke Mehrtens
parent
2e3af78447
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ac96a1665a
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@ -1,32 +1,26 @@
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From 26023cdfacaf116545b1087b9d1fe50dc6fbda10 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
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Date: Wed, 24 Sep 2014 22:14:07 +0200
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Subject: [PATCH] ARM: BCM5301X: Disable MMU and Dcache for decompression
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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From: Florian Fainelli <f.fainelli@gmail.com>
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Subject: [PATCH] ARM: BCM5301x: Disable MMU and Dcache during decompression
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Date: Tue, 14 Jul 2015 16:12:08 -0700
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Without this fix kernel was randomly hanging in ~25% of tries during
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early init. Hangs used to happen at random places in the start_kernel.
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Use the existing __armv7_mmu_cache_flush() to perform the cache flush
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since this does what we are after.
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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---
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arch/arm/boot/compressed/Makefile | 5 +
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arch/arm/boot/compressed/head-bcm_5301x-mpcore.S | 37 +++++++
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arch/arm/boot/compressed/mpcore_cache.S | 118 +++++++++++++++++++++++
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3 files changed, 160 insertions(+)
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arch/arm/boot/compressed/Makefile | 4 +++
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arch/arm/boot/compressed/head-bcm_5301x-mpcore.S | 37 ++++++++++++++++++++++++
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arch/arm/boot/compressed/head.S | 2 ++
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3 files changed, 43 insertions(+)
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create mode 100644 arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
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create mode 100644 arch/arm/boot/compressed/mpcore_cache.S
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--- a/arch/arm/boot/compressed/Makefile
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+++ b/arch/arm/boot/compressed/Makefile
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@@ -31,6 +31,11 @@ ifeq ($(CONFIG_ARCH_ACORN),y)
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@@ -31,6 +31,10 @@ ifeq ($(CONFIG_ARCH_ACORN),y)
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OBJS += ll_char_wr.o font.o
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endif
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+ifeq ($(CONFIG_ARCH_BCM_5301X),y)
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+OBJS += head-bcm_5301x-mpcore.o
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+OBJS += mpcore_cache.o
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+endif
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+
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ifeq ($(CONFIG_ARCH_SA1100),y)
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@ -63,7 +57,7 @@ Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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+ nop
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+
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+ @ Call the cache invalidation routine
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+ bl v7_all_dcache_invalidate
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+ bl __armv7_mmu_cache_flush_fn
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+ nop
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+ mov r0,#0
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+ ldr r3, =0x19022000 @ L2 cache controller, control reg
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@ -72,124 +66,21 @@ Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
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+
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+ @ Restore
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+ mov r8, r12
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--- /dev/null
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+++ b/arch/arm/boot/compressed/mpcore_cache.S
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@@ -0,0 +1,118 @@
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+/*****************************************************************************
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+* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
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+*
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+* Unless you and Broadcom execute a separate written software license
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+* agreement governing use of this software, this software is licensed to you
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+* under the terms of the GNU General Public License version 2, available at
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+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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+*
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+* Notwithstanding the above, under no circumstances may you combine this
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+* software in any way with any other Broadcom software provided under a
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+* license other than the GPL, without Broadcom's express prior written
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+* consent.
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+*****************************************************************************/
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+
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+#include <linux/linkage.h>
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+#include <linux/init.h>
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+
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+ __INIT
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+
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+/*
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+ * v7_l1_cache_invalidate
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+ *
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+ * Invalidate contents of L1 cache without flushing its contents
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+ * into outer cache and memory. This is needed when the contents
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+ * of the cache are unpredictable after power-up.
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+ *
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+ * corrupts r0-r6
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+ */
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+
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+ENTRY(v7_l1_cache_invalidate)
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+ mov r0, #0
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+ mcr p15, 2, r0, c0, c0, 0 @ set cache level to 1
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+ mrc p15, 1, r0, c0, c0, 0 @ read CLIDR
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+
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+ ldr r1, =0x7fff
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+ and r2, r1, r0, lsr #13 @ get max # of index size
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+
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+ ldr r1, =0x3ff
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+ and r3, r1, r0, lsr #3 @ NumWays - 1
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+ add r2, r2, #1 @ NumSets
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+
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+ and r0, r0, #0x7
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+ add r0, r0, #4 @ SetShift
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+
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+ clz r1, r3 @ WayShift
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+ add r4, r3, #1 @ NumWays
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+1: sub r2, r2, #1 @ NumSets--
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+ mov r3, r4 @ Temp = NumWays
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+2: subs r3, r3, #1 @ Temp--
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+ mov r5, r3, lsl r1
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+ mov r6, r2, lsl r0
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+ orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
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+ mcr p15, 0, r5, c7, c6, 2 @ Invalidate line
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+ bgt 2b
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+ cmp r2, #0
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+ bgt 1b
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+ dsb
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+ mov r0,#0
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+ mcr p15,0,r0,c7,c5,0 /* Invalidate icache */
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+ isb
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+ mov pc, lr
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+ENDPROC(v7_l1_cache_invalidate)
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+
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+/*
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+ * v7_all_dcache_invalidate
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+ *
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+ * Invalidate without flushing the contents of all cache levels
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+ * accesible by the current processor core.
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+ * This is useful when the contents of cache memory are undetermined
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+ * at power-up.
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+ * Corrupted registers: r0-r7, r9-r11
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+ *
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+ * Based on cache-v7.S: v7_flush_dcache_all()
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+ */
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+
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+ENTRY(v7_all_dcache_invalidate)
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+ mrc p15, 1, r0, c0, c0, 1 @ read clidr
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+ ands r3, r0, #0x7000000 @ extract loc from clidr
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+ mov r3, r3, lsr #23 @ left align loc bit field
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+ beq finished @ if loc is 0, then no need to clean
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+ mov r10, #0 @ start clean at cache level 0
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+loop1:
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+ add r2, r10, r10, lsr #1 @ work out 3x current cache level
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+ mov r1, r0, lsr r2 @ extract cache type bits from clidr
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+ and r1, r1, #7 @ mask of bits for current cache only
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+ cmp r1, #2 @ see what cache we have at this level
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+ blt skip @ skip if no cache, or just i-cache
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+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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+ isb @ isb to sych the new cssr&csidr
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+ mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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+ and r2, r1, #7 @ extract the length of the cache lines
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+ add r2, r2, #4 @ add 4 (line length offset)
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+ ldr r4, =0x3ff
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+ ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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+ clz r5, r4 @ find bit pos of way size increment
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+ ldr r7, =0x7fff
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+ ands r7, r7, r1, lsr #13 @ extract max number of the index size
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+loop2:
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+ mov r9, r4 @ create working copy of max way size
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+loop3:
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+ orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
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+ orr r11, r11, r7, lsl r2 @ factor index number into r11
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+ mcr p15, 0, r11, c7, c6, 2 @ Invalidate line
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+ subs r9, r9, #1 @ decrement the way
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+ bge loop3
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+ subs r7, r7, #1 @ decrement the index
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+ bge loop2
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+skip:
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+ add r10, r10, #2 @ increment cache number
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+ cmp r3, r10
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+ bgt loop1
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+finished:
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+ mov r10, #0 @ swith back to cache level 0
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+ mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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+ dsb
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+ isb
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+ mov pc, lr
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+ENDPROC(v7_all_dcache_invalidate)
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--- a/arch/arm/boot/compressed/head.S
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+++ b/arch/arm/boot/compressed/head.S
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@@ -1152,6 +1152,7 @@ __armv7_mmu_cache_flush:
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hierarchical:
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mcr p15, 0, r10, c7, c10, 5 @ DMB
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stmfd sp!, {r0-r7, r9-r11}
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+ENTRY(__armv7_mmu_cache_flush_fn)
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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@@ -1201,6 +1202,7 @@ iflush:
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mcr p15, 0, r10, c7, c10, 4 @ DSB
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mcr p15, 0, r10, c7, c5, 4 @ ISB
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mov pc, lr
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+ENDPROC(__armv7_mmu_cache_flush_fn)
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__armv5tej_mmu_cache_flush:
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tst r4, #1
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