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sunxi: make patches apply cleanly on 5.4
These patches are already in mainline 5.4 kernel: * 010-v5.3-drivers-ata-ahci_sunxi-Increased-SATA-AHCI-DMA-TX-RX.patch * 101-arm64-dts-allwinner-a64-Enable-A64-timer-workaround.patch Signed-off-by: Aleksander Jan Bajkowski <A.Bajkowski@stud.elka.pw.edu.pl>
This commit is contained in:
Aleksander Jan Bajkowski
Petr Štetiar
parent
f9bdacc5f6
commit
9883d5d084
@ -1,94 +0,0 @@
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From 120357ea176e420d313cf8cf2ff35fbe233d3bab Mon Sep 17 00:00:00 2001
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From: Uenal Mutlu <um@mutluit.com>
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Date: Mon, 13 May 2019 16:24:10 +0200
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Subject: [PATCH] drivers: ata: ahci_sunxi: Increased SATA/AHCI DMA TX/RX FIFOs
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Increasing the SATA/AHCI DMA TX/RX FIFOs (P0DMACR.TXTS and .RXTS, ie.
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TX_TRANSACTION_SIZE and RX_TRANSACTION_SIZE) from default 0x0 each
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to 0x3 each, gives a write performance boost of 120 MiB/s to 132 MiB/s
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from lame 36 MiB/s to 45 MiB/s previously.
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Read performance is above 200 MiB/s.
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[tested on SSD using dd bs=4K/8K/12K/16K/20K/24K/32K: peak-perf at 12K]
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Tested on the SBCs Banana Pi R1 (aka Lamobo R1) and Banana Pi M1 which
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are based on the Allwinner A20 32bit-SoC (ARMv7-a / arm-linux-gnueabihf).
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These devices are RaspberryPi-like small devices.
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This problem of slow SATA write-speed with these small devices lasts
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for about 7 years now (beginning with the A10 SoC). Many commentators
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throughout the years wrongly assumed the slow write speed was a
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hardware limitation. This patch finally solves the problem, which
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in fact was just a hard-to-find software problem due to lack of
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SATA/AHCI documentation by the SoC-maker Allwinner Technology.
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Lists of the affected sunxi and other boards and SoCs with SATA using
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the ahci_sunxi driver:
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$ grep -i -e "^&ahci" arch/arm/boot/dts/sun*dts
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and http://linux-sunxi.org/SATA#Devices_with_SATA_ports
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See also http://linux-sunxi.org/Category:Devices_with_SATA_port
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Tested-by: Chen-Yu Tsai <wens@csie.org>
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Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Reviewed-by: Hans de Goede <hdegoede@redhat.com>
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Signed-off-by: Uenal Mutlu <um@mutluit.com>
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Signed-off-by: Jens Axboe <axboe@kernel.dk>
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---
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drivers/ata/ahci_sunxi.c | 47 ++++++++++++++++++++++++++++++++++++++--
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1 file changed, 45 insertions(+), 2 deletions(-)
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--- a/drivers/ata/ahci_sunxi.c
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+++ b/drivers/ata/ahci_sunxi.c
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@@ -157,8 +157,51 @@ static void ahci_sunxi_start_engine(stru
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void __iomem *port_mmio = ahci_port_base(ap);
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struct ahci_host_priv *hpriv = ap->host->private_data;
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- /* Setup DMA before DMA start */
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- sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
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+ /* Setup DMA before DMA start
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+ *
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+ * NOTE: A similar SoC with SATA/AHCI by Texas Instruments documents
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+ * this Vendor Specific Port (P0DMACR, aka PxDMACR) in its
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+ * User's Guide document (TMS320C674x/OMAP-L1x Processor
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+ * Serial ATA (SATA) Controller, Literature Number: SPRUGJ8C,
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+ * March 2011, Chapter 4.33 Port DMA Control Register (P0DMACR),
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+ * p.68, https://www.ti.com/lit/ug/sprugj8c/sprugj8c.pdf)
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+ * as equivalent to the following struct:
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+ *
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+ * struct AHCI_P0DMACR_t
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+ * {
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+ * unsigned TXTS : 4;
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+ * unsigned RXTS : 4;
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+ * unsigned TXABL : 4;
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+ * unsigned RXABL : 4;
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+ * unsigned Reserved : 16;
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+ * };
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+ *
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+ * TXTS: Transmit Transaction Size (TX_TRANSACTION_SIZE).
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+ * This field defines the DMA transaction size in DWORDs for
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+ * transmit (system bus read, device write) operation. [...]
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+ *
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+ * RXTS: Receive Transaction Size (RX_TRANSACTION_SIZE).
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+ * This field defines the Port DMA transaction size in DWORDs
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+ * for receive (system bus write, device read) operation. [...]
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+ *
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+ * TXABL: Transmit Burst Limit.
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+ * This field allows software to limit the VBUSP master read
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+ * burst size. [...]
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+ *
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+ * RXABL: Receive Burst Limit.
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+ * Allows software to limit the VBUSP master write burst
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+ * size. [...]
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+ *
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+ * Reserved: Reserved.
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+ *
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+ *
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+ * NOTE: According to the above document, the following alternative
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+ * to the code below could perhaps be a better option
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+ * (or preparation) for possible further improvements later:
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+ * sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff,
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+ * 0x00000033);
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+ */
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+ sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ffff, 0x00004433);
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/* Start DMA */
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sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
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@ -1,26 +0,0 @@
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From 55ec26d6a4241363fa94f15377ebd8f1116fbfd7 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sat, 12 Jan 2019 20:17:19 -0600
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Subject: [PATCH] arm64: dts: allwinner: a64: Enable A64 timer workaround
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As instability in the architectural timer has been observed on multiple
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devices using this SoC, inluding the Pine64 and the Orange Pi Win,
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enable the workaround in the SoC's device tree.
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Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
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1 file changed, 1 insertion(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -159,6 +159,7 @@
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timer {
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compatible = "arm,armv8-timer";
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+ allwinner,erratum-unknown1;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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@ -15,10 +15,10 @@ This reverts commit d7b9eaff5f0ca00726336b4c0c3c29decf30412a.
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--- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
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+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
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@@ -124,67 +124,13 @@
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@@ -120,65 +120,13 @@
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&gmac {
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pinctrl-names = "default";
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pinctrl-0 = <&gmac_pins_rgmii_a>;
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pinctrl-0 = <&gmac_rgmii_pins>;
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+ phy = <&phy1>;
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phy-mode = "rgmii";
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phy-supply = <®_gmac_3v3>;
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@ -37,8 +37,6 @@ This reverts commit d7b9eaff5f0ca00726336b4c0c3c29decf30412a.
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- switch: ethernet-switch@1e {
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- compatible = "brcm,bcm53125";
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- reg = <30>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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-
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- ports {
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- #address-cells = <1>;
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@ -15,7 +15,7 @@ Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
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@@ -78,6 +78,28 @@
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@@ -82,6 +82,28 @@
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>;
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