mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2024-12-22 22:54:06 +00:00
oxnas: move PCIe controller outside of simple-bus
Move PCIe controller outside down to SoC level to avoid resource mapping problems. Also add more detailed error handling when mapping registers. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
parent
a18d41996e
commit
8ad0ba3a07
@ -420,34 +420,51 @@ oxnas_pcie_map_registers(struct platform_device *pdev,
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u32 pcie_ctrl_offset;
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u32 pcie_ctrl_offset;
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ret = of_address_to_resource(np, 0, ®s);
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ret = of_address_to_resource(np, 0, ®s);
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if (ret)
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if (ret) {
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dev_err(&pdev->dev, "failed to parse base register space\n");
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return -EINVAL;
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return -EINVAL;
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}
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pcie->base = devm_ioremap_resource(&pdev->dev, ®s);
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pcie->base = devm_ioremap_resource(&pdev->dev, ®s);
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if (!pcie->base)
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if (!pcie->base) {
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dev_err(&pdev->dev, "failed to map base register space\n");
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return -ENOMEM;
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return -ENOMEM;
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}
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ret = of_address_to_resource(np, 1, ®s);
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ret = of_address_to_resource(np, 1, ®s);
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if (ret)
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if (ret) {
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dev_err(&pdev->dev, "failed to parse inbound register space\n");
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return -EINVAL;
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return -EINVAL;
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}
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pcie->inbound = devm_ioremap_resource(&pdev->dev, ®s);
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pcie->inbound = devm_ioremap_resource(&pdev->dev, ®s);
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if (!pcie->inbound)
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if (!pcie->inbound) {
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dev_err(&pdev->dev, "failed to map inbound register space\n");
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return -ENOMEM;
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return -ENOMEM;
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}
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pcie->phy = devm_of_phy_get(&pdev->dev, np, NULL);
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pcie->phy = devm_of_phy_get(&pdev->dev, np, NULL);
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if (IS_ERR(pcie->phy)) {
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if (IS_ERR(pcie->phy)) {
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if (PTR_ERR(pcie->phy) == -EPROBE_DEFER)
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if (PTR_ERR(pcie->phy) == -EPROBE_DEFER) {
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dev_err(&pdev->dev, "failed to probe phy\n");
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return PTR_ERR(pcie->phy);
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return PTR_ERR(pcie->phy);
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}
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dev_warn(&pdev->dev, "phy not attached\n");
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pcie->phy = NULL;
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pcie->phy = NULL;
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}
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}
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if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
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if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
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&outbound_ctrl_offset))
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&outbound_ctrl_offset)) {
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dev_err(&pdev->dev, "failed to parse outbound register offset\n");
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return -EINVAL;
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return -EINVAL;
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}
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pcie->outbound_offset = outbound_ctrl_offset;
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pcie->outbound_offset = outbound_ctrl_offset;
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if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
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if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
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&pcie_ctrl_offset))
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&pcie_ctrl_offset)) {
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dev_err(&pdev->dev, "failed to parse pcie-ctrl register offset\n");
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return -EINVAL;
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return -EINVAL;
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}
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pcie->pcie_ctrl_offset = pcie_ctrl_offset;
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pcie->pcie_ctrl_offset = pcie_ctrl_offset;
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return 0;
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return 0;
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@ -22,93 +22,99 @@
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--- a/arch/arm/boot/dts/ox820.dtsi
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--- a/arch/arm/boot/dts/ox820.dtsi
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+++ b/arch/arm/boot/dts/ox820.dtsi
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+++ b/arch/arm/boot/dts/ox820.dtsi
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@@ -316,6 +316,89 @@
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@@ -288,7 +288,7 @@
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reg = <0x1000 0x1000>,
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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- ranges = <0 0x47000000 0x1000000>;
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+ ranges = <0 0x47000000 0x2000>;
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scu: scu@0 {
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compatible = "arm,arm11mp-scu";
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@@ -317,5 +317,86 @@
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<0x100 0x500>;
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<0x100 0x500>;
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};
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};
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+
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+ pcie0: pcie-controller@c00000 {
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+ compatible = "plxtech,nas782x-pcie";
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+ device_type = "pci";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ /* flag & space bus address host address size */
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+ ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000
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+ 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000
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+ 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000
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+ 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>;
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+
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+ bus-range = <0x00 0x7f>;
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+
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+ /* cfg inbound translator */
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+ reg = <0xc00000 0x1000>, <0xd00000 0x100>;
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+
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+ phys = <&pcie_phy>;
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+ phy-names = "pcie-phy";
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+
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+ #interrupt-cells = <1>;
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+ /* wild card mask, match all bus address & interrupt specifier */
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+ /* format: bus address mask, interrupt specifier mask */
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+ /* each bit 1 means need match, 0 means ignored when match */
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+ interrupt-map-mask = <0 0 0 0>;
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+ /* format: a list of: bus address, interrupt specifier,
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+ * parent interrupt controller & specifier */
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+ interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
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+
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+ gpios = <&gpio1 12 0>;
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+ clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
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+ clock-names = "pcie", "busclk";
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+ resets = <&reset RESET_PCIEA>;
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+ reset-names = "pcie";
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+
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+ plxtech,pcie-hcsl-bit = <2>;
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+ plxtech,pcie-ctrl-offset = <0x120>;
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+ plxtech,pcie-outbound-offset = <0x138>;
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+ status = "disabled";
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+ };
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+
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+ pcie1: pcie-controller@e00000 {
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+ compatible = "plxtech,nas782x-pcie";
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+ device_type = "pci";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ /* flag & space bus address host address size */
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+ ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000
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+ 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000
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+ 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000
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+ 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>;
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+
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+ bus-range = <0x80 0xff>;
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+
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+ /* cfg inbound translator */
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+ reg = <0xe00000 0x1000>, <0xf00000 0x100>;
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+
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+ phys = <&pcie_phy>;
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+ phy-names = "pcie-phy";
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+
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+ #interrupt-cells = <1>;
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+ /* wild card mask, match all bus address & interrupt specifier */
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+ /* format: bus address mask, interrupt specifier mask */
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+ /* each bit 1 means need match, 0 means ignored when match */
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+ interrupt-map-mask = <0 0 0 0>;
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+ /* format: a list of: bus address, interrupt specifier,
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+ * parent interrupt controller & specifier */
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+ interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
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+
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+ /* gpios = <&gpio1 12 0>; */
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+ clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
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+ clock-names = "pcie", "busclk";
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+ resets = <&reset RESET_PCIEB>;
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+ reset-names = "pcie";
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+
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+ plxtech,pcie-hcsl-bit = <3>;
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+ plxtech,pcie-ctrl-offset = <0x124>;
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+ plxtech,pcie-outbound-offset = <0x174>;
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+ status = "disabled";
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+ };
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+
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};
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};
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+
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+ pcie0: pcie-controller@47c00000 {
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+ compatible = "plxtech,nas782x-pcie";
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+ device_type = "pci";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ /* flag & space bus address host address size */
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+ ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000
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+ 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000
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+ 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000
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+ 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>;
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+
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+ bus-range = <0x00 0x7f>;
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+
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+ /* cfg inbound translator */
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+ reg = <0x47c00000 0x1000>, <0x47d00000 0x100>;
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+
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+ phys = <&pcie_phy>;
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+ phy-names = "pcie-phy";
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+
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+ #interrupt-cells = <1>;
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+ /* wild card mask, match all bus address & interrupt specifier */
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+ /* format: bus address mask, interrupt specifier mask */
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+ /* each bit 1 means need match, 0 means ignored when match */
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+ interrupt-map-mask = <0 0 0 0>;
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+ /* format: a list of: bus address, interrupt specifier,
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+ * parent interrupt controller & specifier */
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+ interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
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+ gpios = <&gpio1 12 0>;
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+ clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
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+ clock-names = "pcie", "busclk";
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+ resets = <&reset RESET_PCIEA>;
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+ reset-names = "pcie";
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+
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+ plxtech,pcie-hcsl-bit = <2>;
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+ plxtech,pcie-ctrl-offset = <0x120>;
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+ plxtech,pcie-outbound-offset = <0x138>;
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+ status = "disabled";
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+ };
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+
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+ pcie1: pcie-controller@47e00000 {
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+ compatible = "plxtech,nas782x-pcie";
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+ device_type = "pci";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ /* flag & space bus address host address size */
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+ ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000
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+ 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000
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+ 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000
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+ 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>;
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+
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+ bus-range = <0x80 0xff>;
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+
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+ /* cfg inbound translator */
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+ reg = <0x47e00000 0x1000>, <0x47f00000 0x100>;
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+
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+ phys = <&pcie_phy>;
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+ phy-names = "pcie-phy";
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+
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+ #interrupt-cells = <1>;
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+ /* wild card mask, match all bus address & interrupt specifier */
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+ /* format: bus address mask, interrupt specifier mask */
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+ /* each bit 1 means need match, 0 means ignored when match */
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+ interrupt-map-mask = <0 0 0 0>;
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+ /* format: a list of: bus address, interrupt specifier,
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+ * parent interrupt controller & specifier */
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+ interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
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+
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+ /* gpios = <&gpio1 12 0>; */
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+ clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
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+ clock-names = "pcie", "busclk";
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+ resets = <&reset RESET_PCIEB>;
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+ reset-names = "pcie";
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+
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+ plxtech,pcie-hcsl-bit = <3>;
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+ plxtech,pcie-ctrl-offset = <0x124>;
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+ plxtech,pcie-outbound-offset = <0x174>;
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+ status = "disabled";
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+ };
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};
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};
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};
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};
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@ -26,9 +26,9 @@
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obj-$(CONFIG_PATA_ALI) += pata_ali.o
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obj-$(CONFIG_PATA_ALI) += pata_ali.o
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--- a/arch/arm/boot/dts/ox820.dtsi
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--- a/arch/arm/boot/dts/ox820.dtsi
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+++ b/arch/arm/boot/dts/ox820.dtsi
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+++ b/arch/arm/boot/dts/ox820.dtsi
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@@ -400,5 +400,20 @@
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@@ -398,5 +398,20 @@
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};
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plxtech,pcie-outbound-offset = <0x174>;
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status = "disabled";
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};
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};
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+
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+
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+ sata: sata@45900000 {
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+ sata: sata@45900000 {
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