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realtek: Replace the RTL9300 generic timer with a CEVT timer
The RTL9300 has a broken R4K MIPS timer interrupt, however, the R4K clocksource works. We replace the RTL9300 timer with a Clock Event Timer (CEVT), which is VSMP aware and can be instantiated as part of brining a VSMTP cpu up instead of the R4K CEVT source. For this we place the RTL9300 CEVT timer in arch/mips/kernel together with other MIPS CEVT timers, initialize the SoC IRQs from a modified smp-mt.c and instantiate each timer as part of the MIPS time setup in arch/mips/include/asm/time.h instead of the R4K CEVT, similarly as is done by other MIPS CEVT timers. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
This commit is contained in:
Birger Koblitz
Daniel Golle
parent
0536c582e6
commit
775d903216
212
target/linux/realtek/files-5.10/arch/mips/kernel/cevt-rtl9300.c
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212
target/linux/realtek/files-5.10/arch/mips/kernel/cevt-rtl9300.c
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@ -0,0 +1,212 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <asm/time.h>
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#include <asm/idle.h>
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#include <linux/interrupt.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <mach-rtl83xx.h>
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/*
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* Timer registers
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* the RTL9300/9310 SoCs have 6 timers, each register block 0x10 apart
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*/
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#define RTL9300_TC_DATA 0x0
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#define RTL9300_TC_CNT 0x4
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#define RTL9300_TC_CTRL 0x8
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#define RTL9300_TC_CTRL_MODE BIT(24)
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#define RTL9300_TC_CTRL_EN BIT(28)
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#define RTL9300_TC_INT 0xc
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#define RTL9300_TC_INT_IP BIT(16)
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#define RTL9300_TC_INT_IE BIT(20)
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// Clocksource is using timer 0, clock event uses timer 1
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#define TIMER_CLK_SRC 0
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#define TIMER_CLK_EVT 0
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#define TIMER_BLK_EVT (TIMER_CLK_EVT << 4)
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// Timer modes
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#define TIMER_MODE_REPEAT 1
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#define TIMER_MODE_ONCE 0
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// Minimum divider is 2
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#define DIVISOR_RTL9300 2
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#define N_BITS 28
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#define RTL9300_TC1_IRQ 8
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#define RTL9300_CLOCK_RATE 87500000
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#define RTL9300_TC0_BASE (void *)0xb8003200
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int irq_tc0 = 7;
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static void __iomem *rtl9300_tc_base(struct clock_event_device *clk)
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{
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struct irq_desc *desc = irq_to_desc(clk->irq);
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int tc = desc->irq_data.hwirq - irq_tc0;
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return RTL9300_TC0_BASE + (tc << 4);
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}
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static irqreturn_t rtl9300_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *clk = dev_id;
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// int cpu = smp_processor_id();
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struct irq_desc *desc = irq_to_desc(irq);
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int tc = desc->irq_data.hwirq - irq_tc0;
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void __iomem *base = RTL9300_TC0_BASE + (tc << 4);
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static atomic_t count = ATOMIC_INIT(0);
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unsigned int c;
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u32 v = readl(base + RTL9300_TC_INT);
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c = (unsigned int)atomic_inc_return(&count);
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// Acknowledge the IRQ
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v |= RTL9300_TC_INT_IP;
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writel(v, base + RTL9300_TC_INT);
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if (readl(base + RTL9300_TC_INT) & RTL9300_TC_INT_IP)
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dump_stack();
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clk->event_handler(clk);
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return IRQ_HANDLED;
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}
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static void rtl9300_clock_stop(void __iomem *base)
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{
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u32 v;
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writel(0, base + RTL9300_TC_CTRL);
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// Acknowledge possibly pending IRQ
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v = readl(base + RTL9300_TC_INT);
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// if (v & RTL9300_TC_INT_IP)
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writel(v | RTL9300_TC_INT_IP, base + RTL9300_TC_INT);
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if (readl(base + RTL9300_TC_INT) & RTL9300_TC_INT_IP)
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dump_stack();
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}
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static void rtl9300_timer_start(void __iomem *base, bool periodic)
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{
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u32 v = (periodic ? RTL9300_TC_CTRL_MODE : 0) | RTL9300_TC_CTRL_EN | DIVISOR_RTL9300;
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writel(0, base + RTL9300_TC_CNT);
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pr_debug("------------- starting timer base %08x\n", (u32)base);
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writel(v, base + RTL9300_TC_CTRL);
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}
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static int rtl9300_next_event(unsigned long delta, struct clock_event_device *clk)
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{
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void __iomem *base = rtl9300_tc_base(clk);
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rtl9300_clock_stop(base);
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writel(delta, base + RTL9300_TC_DATA);
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rtl9300_timer_start(base, TIMER_MODE_ONCE);
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return 0;
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}
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static int rtl9300_state_periodic(struct clock_event_device *clk)
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{
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void __iomem *base = rtl9300_tc_base(clk);
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pr_debug("------------- rtl9300_state_periodic %08x\n", (u32)base);
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rtl9300_clock_stop(base);
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writel(RTL9300_CLOCK_RATE / HZ, base + RTL9300_TC_DATA);
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rtl9300_timer_start(base, TIMER_MODE_REPEAT);
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return 0;
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}
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static int rtl9300_state_oneshot(struct clock_event_device *clk)
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{
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void __iomem *base = rtl9300_tc_base(clk);
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pr_debug("------------- rtl9300_state_oneshot %08x\n", (u32)base);
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rtl9300_clock_stop(base);
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writel(RTL9300_CLOCK_RATE / HZ, base + RTL9300_TC_DATA);
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rtl9300_timer_start(base, TIMER_MODE_ONCE);
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return 0;
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}
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static int rtl9300_shutdown(struct clock_event_device *clk)
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{
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void __iomem *base = rtl9300_tc_base(clk);
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pr_debug("------------- rtl9300_shutdown %08x\n", (u32)base);
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rtl9300_clock_stop(base);
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return 0;
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}
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static void rtl9300_clock_setup(void __iomem *base)
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{
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u32 v;
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// Disable timer
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writel(0, base + RTL9300_TC_CTRL);
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// Acknowledge possibly pending IRQ
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v = readl(base + RTL9300_TC_INT);
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// if (v & RTL9300_TC_INT_IP)
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writel(v | RTL9300_TC_INT_IP, base + RTL9300_TC_INT);
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if (readl(base + RTL9300_TC_INT) & RTL9300_TC_INT_IP)
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dump_stack();
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// Setup maximum period (for use as clock-source)
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writel(0x0fffffff, base + RTL9300_TC_DATA);
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}
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static DEFINE_PER_CPU(struct clock_event_device, rtl9300_clockevent);
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static DEFINE_PER_CPU(char [18], rtl9300_clock_name);
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void rtl9300_clockevent_init(void)
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{
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int cpu = smp_processor_id();
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int irq;
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struct clock_event_device *cd = &per_cpu(rtl9300_clockevent, cpu);
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unsigned char *name = per_cpu(rtl9300_clock_name, cpu);
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unsigned long flags = IRQF_PERCPU | IRQF_TIMER;
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struct device_node *node;
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pr_info("%s called for cpu%d\n", __func__, cpu);
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BUG_ON(cpu > 3); /* Only have 4 general purpose timers */
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node = of_find_compatible_node(NULL, NULL, "realtek,rtl9300clock");
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if (!node) {
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pr_err("No DT entry found for realtek,rtl9300clock\n");
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return;
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}
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irq = irq_of_parse_and_map(node, cpu);
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pr_info("%s using IRQ %d\n", __func__, irq);
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rtl9300_clock_setup(RTL9300_TC0_BASE + TIMER_BLK_EVT + (cpu << 4));
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sprintf(name, "rtl9300-counter-%d", cpu);
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cd->name = name;
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cd->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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clockevent_set_clock(cd, RTL9300_CLOCK_RATE);
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cd->max_delta_ns = clockevent_delta2ns(0x0fffffff, cd);
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cd->max_delta_ticks = 0x0fffffff;
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cd->min_delta_ns = clockevent_delta2ns(0x20, cd);
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cd->min_delta_ticks = 0x20;
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cd->rating = 300;
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cd->irq = irq;
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cd->cpumask = cpumask_of(cpu);
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cd->set_next_event = rtl9300_next_event;
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cd->set_state_shutdown = rtl9300_shutdown;
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cd->set_state_periodic = rtl9300_state_periodic;
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cd->set_state_oneshot = rtl9300_state_oneshot;
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clockevents_register_device(cd);
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irq_set_affinity(irq, cd->cpumask);
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if (request_irq(irq, rtl9300_timer_interrupt, flags, name, cd))
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pr_err("Failed to request irq %d (%s)\n", irq, name);
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writel(RTL9300_TC_INT_IE, RTL9300_TC0_BASE + TIMER_BLK_EVT + (cpu << 4) + RTL9300_TC_INT);
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}
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@ -1,196 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <asm/time.h>
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#include <linux/interrupt.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include "timer-of.h"
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#include <mach-rtl83xx.h>
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/*
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* Timer registers
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* the RTL9300/9310 SoCs have 6 timers, each register block 0x10 apart
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*/
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#define RTL9300_TC_DATA 0x0
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#define RTL9300_TC_CNT 0x4
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#define RTL9300_TC_CTRL 0x8
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#define RTL9300_TC_CTRL_MODE BIT(24)
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#define RTL9300_TC_CTRL_EN BIT(28)
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#define RTL9300_TC_INT 0xc
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#define RTL9300_TC_INT_IP BIT(16)
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#define RTL9300_TC_INT_IE BIT(20)
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// Clocksource is using timer 0, clock event uses timer 1
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#define TIMER_CLK_SRC 0
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#define TIMER_CLK_EVT 1
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#define TIMER_BLK_EVT (TIMER_CLK_EVT << 4)
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// Timer modes
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#define TIMER_MODE_REPEAT 1
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#define TIMER_MODE_ONCE 0
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// Minimum divider is 2
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#define DIVISOR_RTL9300 2
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#define N_BITS 28
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static void __iomem *rtl9300_sched_reg __read_mostly;
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static u64 notrace rtl9300_sched_clock_read(void)
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{
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/* pr_info("In %s: %x\n", __func__, readl_relaxed(rtl9300_sched_reg));
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dump_stack();*/
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return readl_relaxed(rtl9300_sched_reg);
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}
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static irqreturn_t rtl9300_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *clk = dev_id;
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struct timer_of *to = to_timer_of(clk);
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u32 v = readl(timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
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// Acknowledge the IRQ
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v |= RTL9300_TC_INT_IP;
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writel(v, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
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clk->event_handler(clk);
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return IRQ_HANDLED;
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}
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static void rtl9300_timer_stop(struct timer_of *to)
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{
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u32 v;
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writel(0, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_CTRL);
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// Acknowledge possibly pending IRQ
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v = readl(timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
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if (v & RTL9300_TC_INT_IP)
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writel(v, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_INT);
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}
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static void rtl9300_timer_start(struct timer_of *to, int timer, bool periodic)
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{
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u32 v = (periodic ? RTL9300_TC_CTRL_MODE : 0) | RTL9300_TC_CTRL_EN | DIVISOR_RTL9300;
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writel(v, timer_of_base(to) + timer * 0x10 + RTL9300_TC_CTRL);
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}
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static int rtl9300_set_next_event(unsigned long delta, struct clock_event_device *clk)
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{
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struct timer_of *to = to_timer_of(clk);
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rtl9300_timer_stop(to);
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writel(delta, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA);
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rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_ONCE);
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return 0;
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}
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static int rtl9300_set_state_periodic(struct clock_event_device *clk)
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{
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struct timer_of *to = to_timer_of(clk);
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rtl9300_timer_stop(to);
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writel(to->of_clk.period, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA);
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rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_REPEAT);
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return 0;
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}
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static int rtl9300_set_state_oneshot(struct clock_event_device *clk)
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{
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struct timer_of *to = to_timer_of(clk);
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rtl9300_timer_stop(to);
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writel(to->of_clk.period, timer_of_base(to) + TIMER_BLK_EVT + RTL9300_TC_DATA);
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rtl9300_timer_start(to, TIMER_CLK_EVT, TIMER_MODE_ONCE);
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return 0;
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}
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static int rtl9300_set_state_shutdown(struct clock_event_device *clk)
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{
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struct timer_of *to = to_timer_of(clk);
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rtl9300_timer_stop(to);
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return 0;
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}
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static struct timer_of t_of = {
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.flags = TIMER_OF_BASE | TIMER_OF_IRQ | TIMER_OF_CLOCK,
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.clkevt = {
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.name = "rtl9300_timer",
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.rating = 350,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = rtl9300_set_next_event,
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.set_state_oneshot = rtl9300_set_state_oneshot,
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.set_state_periodic = rtl9300_set_state_periodic,
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.set_state_shutdown = rtl9300_set_state_shutdown,
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},
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.of_irq = {
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.name = "ostimer",
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.handler = rtl9300_timer_interrupt,
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.flags = IRQF_TIMER,
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},
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};
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static void __init rtl9300_timer_setup(u8 timer)
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{
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u32 v;
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// Disable timer
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writel(0, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_CTRL);
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// Acknowledge possibly pending IRQ
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v = readl(timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_INT);
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if (v & RTL9300_TC_INT_IP)
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writel(v, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_INT);
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// Setup maximum period (for use as clock-source)
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writel(0x0fffffff, timer_of_base(&t_of) + 0x10 * timer + RTL9300_TC_DATA);
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}
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static int __init rtl9300_timer_init(struct device_node *node)
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{
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int err = 0;
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unsigned long rate;
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pr_info("%s: setting up timer\n", __func__);
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err = timer_of_init(node, &t_of);
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if (err)
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return err;
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rate = timer_of_rate(&t_of) / DIVISOR_RTL9300;
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pr_info("Frequency in dts: %ld, my rate is %ld, period %ld\n",
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timer_of_rate(&t_of), rate, timer_of_period(&t_of));
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pr_info("With base %08x IRQ: %d\n", (u32)timer_of_base(&t_of), timer_of_irq(&t_of));
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// Configure clock source and register it for scheduling
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rtl9300_timer_setup(TIMER_CLK_SRC);
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rtl9300_timer_start(&t_of, TIMER_CLK_SRC, TIMER_MODE_REPEAT);
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rtl9300_sched_reg = timer_of_base(&t_of) + TIMER_CLK_SRC * 0x10 + RTL9300_TC_CNT;
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err = clocksource_mmio_init(rtl9300_sched_reg, node->name, rate , 100, N_BITS,
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clocksource_mmio_readl_up);
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if (err)
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return err;
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sched_clock_register(rtl9300_sched_clock_read, N_BITS, rate);
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// Configure clock event source
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rtl9300_timer_setup(TIMER_CLK_EVT);
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clockevents_config_and_register(&t_of.clkevt, rate, 100, 0x0fffffff);
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// Enable interrupt
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writel(RTL9300_TC_INT_IE, timer_of_base(&t_of) + TIMER_BLK_EVT + RTL9300_TC_INT);
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return err;
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}
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||||
|
||||
TIMER_OF_DECLARE(rtl9300_timer, "realtek,rtl9300-timer", rtl9300_timer_init);
|
||||
@ -1,28 +0,0 @@
|
||||
--- a/drivers/clocksource/Kconfig
|
||||
+++ b/drivers/clocksource/Kconfig
|
||||
@@ -127,6 +127,15 @@ config RDA_TIMER
|
||||
help
|
||||
Enables the support for the RDA Micro timer driver.
|
||||
|
||||
+config RTL9300_TIMER
|
||||
+ bool "Clocksource/timer for the Realtek RTL9300 family of SoCs"
|
||||
+ depends on MIPS
|
||||
+ select COMMON_CLK
|
||||
+ select TIMER_OF
|
||||
+ select CLKSRC_MMIO
|
||||
+ help
|
||||
+ Enables support for the Realtek RTL9300 timer driver.
|
||||
+
|
||||
config SUN4I_TIMER
|
||||
bool "Sun4i timer driver" if COMPILE_TEST
|
||||
depends on HAS_IOMEM
|
||||
--- a/drivers/clocksource/Makefile
|
||||
+++ b/drivers/clocksource/Makefile
|
||||
@@ -63,6 +63,7 @@ obj-$(CONFIG_MILBEAUT_TIMER) += timer-mi
|
||||
obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o
|
||||
obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o
|
||||
obj-$(CONFIG_RDA_TIMER) += timer-rda.o
|
||||
+obj-$(CONFIG_RTL9300_TIMER) += timer-rtl9300.o
|
||||
|
||||
obj-$(CONFIG_ARC_TIMERS) += arc_timer.o
|
||||
obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o
|
||||
@ -0,0 +1,54 @@
|
||||
--- a/arch/mips/kernel/Makefile
|
||||
+++ b/arch/mips/kernel/Makefile
|
||||
@@ -27,6 +27,7 @@ obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm14
|
||||
obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
|
||||
obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o
|
||||
obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
|
||||
+obj-$(CONFIG_CEVT_RTL9300) += cevt-rtl9300.o
|
||||
obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
|
||||
obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
|
||||
obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
|
||||
--- a/arch/mips/include/asm/time.h
|
||||
+++ b/arch/mips/include/asm/time.h
|
||||
@@ -15,6 +15,8 @@
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/clocksource.h>
|
||||
|
||||
+extern void rtl9300_clockevent_init(void);
|
||||
+
|
||||
extern spinlock_t rtc_lock;
|
||||
|
||||
/*
|
||||
@@ -43,6 +45,11 @@ extern int r4k_clockevent_init(void);
|
||||
|
||||
static inline int mips_clockevent_init(void)
|
||||
{
|
||||
+#ifdef CONFIG_CEVT_RTL9300
|
||||
+ rtl9300_clockevent_init();
|
||||
+ return 0;
|
||||
+#endif
|
||||
+
|
||||
#ifdef CONFIG_CEVT_R4K
|
||||
return r4k_clockevent_init();
|
||||
#else
|
||||
--- a/arch/mips/kernel/smp-mt.c
|
||||
+++ b/arch/mips/kernel/smp-mt.c
|
||||
@@ -108,12 +108,18 @@ static void __init smvp_tc_init(unsigned
|
||||
static void vsmp_init_secondary(void)
|
||||
{
|
||||
/* This is Malta specific: IPI,performance and timer interrupts */
|
||||
+
|
||||
+ /* RTL9300 Clear internal timer interrupt */
|
||||
+ write_c0_compare(0);
|
||||
+
|
||||
if (mips_gic_present())
|
||||
change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
|
||||
STATUSF_IP4 | STATUSF_IP5 |
|
||||
STATUSF_IP6 | STATUSF_IP7);
|
||||
else
|
||||
change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
|
||||
+ STATUSF_IP2 | STATUSF_IP3 |
|
||||
+ STATUSF_IP4 | STATUSF_IP5 |
|
||||
STATUSF_IP6 | STATUSF_IP7);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user