mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2024-12-12 18:05:15 +00:00
add some fixes for v1 hardware (doesn't work reliably yet)
SVN-Revision: 1100
This commit is contained in:
Felix Fietkau
parent
f129a43a9e
commit
75b3d0473e
@ -0,0 +1,108 @@
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diff -urN linux.old/arch/mips/mm/tlbex-mips32.S linux.dev/arch/mips/mm/tlbex-mips32.S
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--- linux.old/arch/mips/mm/tlbex-mips32.S 2005-05-28 17:42:03.000000000 +0200
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+++ linux.dev/arch/mips/mm/tlbex-mips32.S 2005-05-28 21:48:55.000000000 +0200
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@@ -90,6 +90,9 @@
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.set noat
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LEAF(except_vec0_r4000)
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.set mips3
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+#ifdef CONFIG_BCM4704
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+ nop
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+#endif
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#ifdef CONFIG_SMP
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mfc0 k1, CP0_CONTEXT
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la k0, pgd_current
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diff -urN linux.old/arch/mips/mm/pg-r4k.c linux.dev/arch/mips/mm/pg-r4k.c
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--- linux.old/arch/mips/mm/pg-r4k.c 2005-01-19 15:09:29.000000000 +0100
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+++ linux.dev/arch/mips/mm/pg-r4k.c 2005-05-28 21:57:52.000000000 +0200
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@@ -180,6 +180,7 @@
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static inline void build_cdex_s(void)
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{
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+#if !defined(CONFIG_BCM4704) && !defined(CONFIG_BCM4710)
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union mips_instruction mi;
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if ((store_offset & (cpu_scache_line_size() - 1)))
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@@ -192,10 +193,12 @@
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mi.c_format.simmediate = store_offset;
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emit_instruction(mi);
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+#endif
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}
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static inline void build_cdex_p(void)
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{
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+#if !defined(CONFIG_BCM4704) && !defined(CONFIG_BCM4710)
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union mips_instruction mi;
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if (store_offset & (cpu_dcache_line_size() - 1))
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@@ -218,6 +221,7 @@
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mi.c_format.simmediate = store_offset;
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emit_instruction(mi);
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+#endif
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}
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static void __build_store_reg(int reg)
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diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
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--- linux.old/include/asm-mips/stackframe.h 2002-11-29 00:53:15.000000000 +0100
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+++ linux.dev/include/asm-mips/stackframe.h 2005-05-28 21:53:03.000000000 +0200
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@@ -172,6 +172,46 @@
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rfe; \
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.set pop
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+#elif defined(CONFIG_BCM4710) || defined(CONFIG_BCM4704)
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+
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+#define RESTORE_SOME \
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+ .set push; \
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+ .set reorder; \
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+ mfc0 t0, CP0_STATUS; \
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+ .set pop; \
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+ ori t0, 0x1f; \
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+ xori t0, 0x1f; \
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+ mtc0 t0, CP0_STATUS; \
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+ li v1, 0xff00; \
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+ and t0, v1; \
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+ lw v0, PT_STATUS(sp); \
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+ nor v1, $0, v1; \
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+ and v0, v1; \
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+ or v0, t0; \
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+ ori v1, v0, ST0_IE; \
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+ xori v1, v1, ST0_IE; \
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+ mtc0 v1, CP0_STATUS; \
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+ mtc0 v0, CP0_STATUS; \
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+ lw v1, PT_EPC(sp); \
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+ mtc0 v1, CP0_EPC; \
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+ lw $31, PT_R31(sp); \
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+ lw $28, PT_R28(sp); \
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+ lw $25, PT_R25(sp); \
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+ lw $7, PT_R7(sp); \
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+ lw $6, PT_R6(sp); \
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+ lw $5, PT_R5(sp); \
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+ lw $4, PT_R4(sp); \
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+ lw $3, PT_R3(sp); \
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+ lw $2, PT_R2(sp)
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+
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+#define RESTORE_SP_AND_RET \
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+ lw sp, PT_R29(sp); \
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+ nop; \
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+ nop; \
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+ .set mips3; \
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+ eret; \
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+ .set mips0
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+
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#else
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#define RESTORE_SOME \
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diff -urN linux.old/arch/mips/mm/tlbex-r4k.S linux.dev/arch/mips/mm/tlbex-r4k.S
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--- linux.old/arch/mips/mm/tlbex-r4k.S 2005-05-28 17:42:03.000000000 +0200
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+++ linux.dev/arch/mips/mm/tlbex-r4k.S 2005-05-29 15:04:43.000000000 +0200
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@@ -168,6 +168,9 @@
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.set noat
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LEAF(except_vec0_r4000)
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.set mips3
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+#ifdef CONFIG_BCM4704
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+ nop
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+#endif
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GET_PGD(k0, k1) # get pgd pointer
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mfc0 k0, CP0_BADVADDR # Get faulting address
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srl k0, k0, _PGDIR_SHIFT # get pgd only bits
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147
openwrt/target/linux/linux-2.4/patches/007-bcm94710_mmu.patch
Normal file
147
openwrt/target/linux/linux-2.4/patches/007-bcm94710_mmu.patch
Normal file
@ -0,0 +1,147 @@
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diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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--- linux.old/arch/mips/mm/c-r4k.c 2005-05-28 17:42:06.000000000 +0200
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+++ linux.dev/arch/mips/mm/c-r4k.c 2005-05-29 18:26:34.000000000 +0200
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@@ -14,6 +14,12 @@
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#include <linux/mm.h>
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#include <linux/bitops.h>
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+#ifdef CONFIG_BCM4710
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+#include "../bcm947xx/include/typedefs.h"
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+#include "../bcm947xx/include/sbconfig.h"
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+#include <asm/paccess.h>
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+#endif
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+
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#include <asm/bcache.h>
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#include <asm/bootinfo.h>
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#include <asm/cacheops.h>
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@@ -390,6 +396,11 @@
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addr = start & ~(dc_lsize - 1);
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aend = (end - 1) & ~(dc_lsize - 1);
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+#ifdef CONFIG_BCM4710
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+ BCM4710_FILL_TLB(addr);
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+ BCM4710_FILL_TLB(aend);
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+#endif
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+
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while (1) {
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/* Hit_Writeback_Inv_D */
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protected_writeback_dcache_line(addr);
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@@ -509,6 +520,10 @@
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R4600_HIT_CACHEOP_WAR_IMPL;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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+#ifdef CONFIG_BCM4710
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+ BCM4710_FILL_TLB(a);
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+ BCM4710_FILL_TLB(end);
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+#endif
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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@@ -576,6 +591,10 @@
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unsigned long ic_lsize = current_cpu_data.icache.linesz;
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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+#ifdef CONFIG_BCM4710
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
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+#endif
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R4600_HIT_CACHEOP_WAR_IMPL;
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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protected_flush_icache_line(addr & ~(ic_lsize - 1));
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diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
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--- linux.old/include/asm-mips/r4kcache.h 2005-05-28 17:42:06.000000000 +0200
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+++ linux.dev/include/asm-mips/r4kcache.h 2005-05-29 18:34:46.000000000 +0200
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@@ -15,6 +15,25 @@
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#include <asm/asm.h>
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#include <asm/cacheops.h>
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+#ifdef CONFIG_BCM4710
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+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
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+
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+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
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+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
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+
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+#define cache_op(op,addr) \
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+ BCM4710_DUMMY_RREG(); \
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+ __asm__ __volatile__( \
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+ " .set noreorder \n" \
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+ " .set mips3\n\t \n" \
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+ " cache %0, %1 \n" \
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+ " .set mips0 \n" \
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+ " .set reorder" \
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+ : \
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+ : "i" (op), "m" (*(unsigned char *)(addr)))
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+
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+#else
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+
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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@@ -24,6 +43,8 @@
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" .set reorder" \
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: \
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: "i" (op), "m" (*(unsigned char *)(addr)))
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+#endif
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+
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static inline void flush_icache_line_indexed(unsigned long addr)
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{
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@@ -47,6 +68,10 @@
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static inline void flush_dcache_line(unsigned long addr)
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{
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+
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+#ifdef CONFIG_BCM4710
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+ BCM4710_DUMMY_RREG();
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+#endif
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cache_op(Hit_Writeback_Inv_D, addr);
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}
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@@ -196,7 +221,13 @@
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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+#ifdef CONFIG_BCM4710
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+ BCM4710_FILL_TLB(start);
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+#endif
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do {
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+#ifdef CONFIG_BCM4710
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+ BCM4710_DUMMY_RREG();
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+#endif
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cache16_unroll32(start,Hit_Invalidate_I);
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start += 0x200;
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} while (start < end);
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@@ -291,8 +322,12 @@
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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- for (addr = start; addr < end; addr += 0x400)
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+ for (addr = start; addr < end; addr += 0x400) {
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+#ifdef CONFIG_BCM4710
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+ BCM4710_DUMMY_RREG();
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+#endif
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cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
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+ }
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}
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static inline void blast_dcache32_page(unsigned long page)
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@@ -300,6 +335,9 @@
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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+#ifdef CONFIG_BCM4710
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+ __asm__ __volatile__("nop;nop;nop;nop");
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+#endif
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do {
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cache32_unroll32(start,Hit_Writeback_Inv_D);
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start += 0x400;
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@@ -339,6 +377,9 @@
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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+#ifdef CONFIG_BCM4710
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+ BCM4710_FILL_TLB(start);
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+#endif
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do {
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cache32_unroll32(start,Hit_Invalidate_I);
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start += 0x400;
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