mirror of
git://git.openwrt.org/openwrt/openwrt.git
synced 2025-02-16 20:07:23 +00:00
realtek: add support for HPE 1920-48G (JG927A) and 1920-48G-PoE (JG928A)
Hardware information: --------------------- - SoC: RTL8393M - Copper phy: 6×RTL8218B - Fibre phy: RTL8214FC - Flash: 32MiB SPI NOR, MX25L25635FMI - RAM: 128MiB DDR3, Micron MT41K64M16TW-107 - Serial port: ±5V serial port to RJ45, ZT3232 (MAX3232 compatible) - +370W POE on JG928A model Note: SFP ports currently non-functional due to missing support for RTL8214FC on the RTL8393M target. Updated for Linux 6.6 kernel. Installation: ------------- - Initial installation follows same process as HPE 1920-24G (JG924A) - Based on prior work of Jan Hoffmann <jan@3e8.eu> - Additional work by Andreas Böhler <dev@aboehler.at> - PoE updates and tidy-up by Stephen Howell <howels@allthatwemight.be> Signed-off-by: Stephen Howell <howels@allthatwemight.be>
This commit is contained in:
Stephen Howell
Sander Vanheule
parent
afa9811a0c
commit
732f539fb7
@ -35,7 +35,9 @@ hpe,1920-8g|\
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hpe,1920-8g-poe-65w|\
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hpe,1920-8g-poe-180w|\
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hpe,1920-16g|\
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hpe,1920-24g)
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hpe,1920-24g|\
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hpe,1920-48g|\
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hpe,1920-48g-poe)
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label_mac=$(mtd_get_mac_binary factory 0x68)
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lan_mac=$label_mac
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mac_count1=$(hexdump -v -n 4 -s 0x110 -e '4 "%d"' $(find_mtd_part factory) 2>/dev/null)
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@ -89,6 +91,11 @@ hpe,1920-8g-poe-65w)
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hpe,1920-8g-poe-180w)
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ucidef_set_poe 180 "$(filter_port_list_reverse "$lan_list" "lan9 lan10")"
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;;
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hpe,1920-48g-poe)
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ucidef_set_poe 370 "lan8 lan7 lan6 lan5 lan4 lan3 lan2 lan1 lan16 lan15 lan14 lan13 lan12 lan11 lan10 lan9 lan24 lan23
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lan22 lan21 lan20 lan19 lan18 lan17 lan32 lan31 lan30 lan29 lan28 lan27 lan26 lan25 lan40 lan39 lan38 lan37
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lan36 lan35 lan34 lan33 lan48 lan47 lan46 lan45 lan44 lan43 lan42 lan41"
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;;
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netgear,gs110tpp-v1)
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ucidef_set_poe 130 "$(filter_port_list "$lan_list" "lan9 lan10")"
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;;
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@ -1,7 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl838x.dtsi"
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#include "rtl838x_hpe_1920.dtsi"
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#include "rtl83xx_hpe_1920.dtsi"
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/ {
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gpio1: rtl8231-gpio {
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@ -1,7 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl838x.dtsi"
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#include "rtl838x_hpe_1920.dtsi"
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#include "rtl83xx_hpe_1920.dtsi"
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/ {
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gpio1: rtl8231-gpio {
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12
target/linux/realtek/dts/rtl8393_hpe_1920-48g-poe.dts
Normal file
12
target/linux/realtek/dts/rtl8393_hpe_1920-48g-poe.dts
Normal file
@ -0,0 +1,12 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl8393_hpe_1920.dtsi"
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/ {
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compatible = "hpe,1920-48g-poe", "realtek,rtl8393-soc";
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model = "HPE 1920-48G-PoE (JG928A)";
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};
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&uart1 {
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status = "okay";
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};
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8
target/linux/realtek/dts/rtl8393_hpe_1920-48g.dts
Normal file
8
target/linux/realtek/dts/rtl8393_hpe_1920-48g.dts
Normal file
@ -0,0 +1,8 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl8393_hpe_1920.dtsi"
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/ {
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compatible = "hpe,1920-48g", "realtek,rtl8393-soc";
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model = "HPE 1920-48G (JG927A)";
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};
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246
target/linux/realtek/dts/rtl8393_hpe_1920.dtsi
Normal file
246
target/linux/realtek/dts/rtl8393_hpe_1920.dtsi
Normal file
@ -0,0 +1,246 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "rtl839x.dtsi"
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#include "rtl83xx_hpe_1920.dtsi"
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#include <dt-bindings/leds/common.h>
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/ {
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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leds {
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compatible = "gpio-leds";
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led_power: led-0 {
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label = "green:power";
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_POWER;
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gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
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};
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};
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i2c0: i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio0 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp0: sfp-p49 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 19 GPIO_ACTIVE_LOW>;
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// tx-fault unconnected (TODO?)
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// tx-disable connected to RTL8214FC (TODO?)
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};
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i2c1: i2c-gpio-1 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp1: sfp-p50 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 12 GPIO_ACTIVE_LOW>;
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// tx-fault unconnected (TODO?)
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// tx-disable connected to RTL8214FC (TODO?)
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};
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// not enabled due to shared I2C clock
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i2c2: i2c-gpio-2 {
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status = "disabled";
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compatible = "i2c-gpio";
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sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp2: sfp-p51 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c2>;
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los-gpio = <&gpio0 23 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
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// tx-fault unconnected (TODO?)
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// tx-disable connected to RTL8214FC (TODO?)
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};
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// not enabled due to shared I2C clock
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i2c3: i2c-gpio-3 {
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status = "disabled";
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compatible = "i2c-gpio";
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sda-gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp3: sfp-p52 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c3>;
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los-gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio0 15 GPIO_ACTIVE_LOW>;
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// tx-fault unconnected (TODO?)
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// tx-disable connected to RTL8214FC (TODO?)
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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EXTERNAL_PHY(0)
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EXTERNAL_PHY(1)
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EXTERNAL_PHY(2)
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EXTERNAL_PHY(3)
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EXTERNAL_PHY(4)
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EXTERNAL_PHY(5)
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EXTERNAL_PHY(6)
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EXTERNAL_PHY(7)
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EXTERNAL_PHY(8)
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EXTERNAL_PHY(9)
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EXTERNAL_PHY(10)
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EXTERNAL_PHY(11)
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EXTERNAL_PHY(12)
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EXTERNAL_PHY(13)
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EXTERNAL_PHY(14)
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EXTERNAL_PHY(15)
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EXTERNAL_PHY(16)
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EXTERNAL_PHY(17)
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EXTERNAL_PHY(18)
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EXTERNAL_PHY(19)
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EXTERNAL_PHY(20)
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EXTERNAL_PHY(21)
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EXTERNAL_PHY(22)
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EXTERNAL_PHY(23)
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EXTERNAL_PHY(24)
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EXTERNAL_PHY(25)
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EXTERNAL_PHY(26)
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EXTERNAL_PHY(27)
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EXTERNAL_PHY(28)
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EXTERNAL_PHY(29)
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EXTERNAL_PHY(30)
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EXTERNAL_PHY(31)
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EXTERNAL_PHY(32)
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EXTERNAL_PHY(33)
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EXTERNAL_PHY(34)
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EXTERNAL_PHY(35)
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EXTERNAL_PHY(36)
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EXTERNAL_PHY(37)
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EXTERNAL_PHY(38)
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EXTERNAL_PHY(39)
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EXTERNAL_PHY(40)
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EXTERNAL_PHY(41)
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EXTERNAL_PHY(42)
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EXTERNAL_PHY(43)
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EXTERNAL_PHY(44)
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EXTERNAL_PHY(45)
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EXTERNAL_PHY(46)
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EXTERNAL_PHY(47)
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EXTERNAL_SFP_PHY_FULL(48, 1)
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EXTERNAL_SFP_PHY_FULL(49, 3)
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EXTERNAL_SFP_PHY_FULL(50, 0)
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EXTERNAL_SFP_PHY_FULL(51, 2)
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(0, 1, qsgmii)
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SWITCH_PORT(1, 2, qsgmii)
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SWITCH_PORT(2, 3, qsgmii)
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SWITCH_PORT(3, 4, qsgmii)
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SWITCH_PORT(4, 5, qsgmii)
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SWITCH_PORT(5, 6, qsgmii)
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SWITCH_PORT(6, 7, qsgmii)
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SWITCH_PORT(7, 8, qsgmii)
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SWITCH_PORT(8, 9, qsgmii)
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SWITCH_PORT(9, 10, qsgmii)
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SWITCH_PORT(10, 11, qsgmii)
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SWITCH_PORT(11, 12, qsgmii)
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SWITCH_PORT(12, 13, qsgmii)
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SWITCH_PORT(13, 14, qsgmii)
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SWITCH_PORT(14, 15, qsgmii)
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SWITCH_PORT(15, 16, qsgmii)
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SWITCH_PORT(16, 17, qsgmii)
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SWITCH_PORT(17, 18, qsgmii)
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SWITCH_PORT(18, 19, qsgmii)
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SWITCH_PORT(19, 20, qsgmii)
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SWITCH_PORT(20, 21, qsgmii)
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SWITCH_PORT(21, 22, qsgmii)
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SWITCH_PORT(22, 23, qsgmii)
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SWITCH_PORT(23, 24, qsgmii)
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SWITCH_PORT(24, 25, qsgmii)
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SWITCH_PORT(25, 26, qsgmii)
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SWITCH_PORT(26, 27, qsgmii)
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SWITCH_PORT(27, 28, qsgmii)
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SWITCH_PORT(28, 29, qsgmii)
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SWITCH_PORT(29, 30, qsgmii)
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SWITCH_PORT(30, 31, qsgmii)
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SWITCH_PORT(31, 32, qsgmii)
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SWITCH_PORT(32, 33, qsgmii)
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SWITCH_PORT(33, 34, qsgmii)
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SWITCH_PORT(34, 35, qsgmii)
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SWITCH_PORT(35, 36, qsgmii)
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SWITCH_PORT(36, 37, qsgmii)
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SWITCH_PORT(37, 38, qsgmii)
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SWITCH_PORT(38, 39, qsgmii)
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SWITCH_PORT(39, 40, qsgmii)
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SWITCH_PORT(40, 41, qsgmii)
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SWITCH_PORT(41, 42, qsgmii)
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SWITCH_PORT(42, 43, qsgmii)
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SWITCH_PORT(43, 44, qsgmii)
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SWITCH_PORT(44, 45, qsgmii)
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SWITCH_PORT(45, 46, qsgmii)
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SWITCH_PORT(46, 47, qsgmii)
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SWITCH_PORT(47, 48, qsgmii)
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SWITCH_PORT(48, 50, qsgmii)
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SWITCH_PORT(49, 52, qsgmii)
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SWITCH_PORT(50, 49, qsgmii)
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SWITCH_PORT(51, 51, qsgmii)
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port@52 {
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ethernet = <ðernet0>;
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reg = <52>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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@ -9,6 +9,23 @@ define Device/d-link_dgs-1210-52
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endef
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TARGET_DEVICES += d-link_dgs-1210-52
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define Device/hpe_1920-48g
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$(Device/hpe_1920)
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SOC := rtl8393
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DEVICE_MODEL := 1920-48G (JG927A)
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H3C_DEVICE_ID := 0x0001002a
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endef
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TARGET_DEVICES += hpe_1920-48g
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define Device/hpe_1920-48g-poe
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$(Device/hpe_1920)
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SOC := rtl8393
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DEVICE_MODEL := 1920-48G-PoE (JG928A)
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DEVICE_PACKAGES += realtek-poe
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H3C_DEVICE_ID := 0x0001002b
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endef
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TARGET_DEVICES += hpe_1920-48g-poe
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# When the factory image won't fit anymore, it can be removed.
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# New installation will be performed booting the initramfs image from
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# ram and then flashing the sysupgrade image from OpenWrt
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@ -88,6 +88,8 @@ CONFIG_GPIO_PCA953X=y
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CONFIG_GPIO_PCA953X_IRQ=y
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CONFIG_GPIO_REALTEK_OTTO=y
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CONFIG_GPIO_RTL8231=y
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CONFIG_GPIO_WATCHDOG=y
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# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
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CONFIG_GRO_CELLS=y
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CONFIG_HANDLE_DOMAIN_IRQ=y
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CONFIG_HARDWARE_WATCHPOINTS=y
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@ -150,6 +152,7 @@ CONFIG_MTD_SPI_NOR=y
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CONFIG_MTD_SPLIT_BRNIMAGE_FW=y
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CONFIG_MTD_SPLIT_EVA_FW=y
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CONFIG_MTD_SPLIT_FIRMWARE=y
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CONFIG_MTD_SPLIT_H3C_VFS=y
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CONFIG_MTD_SPLIT_TPLINK_FW=y
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CONFIG_MTD_SPLIT_UIMAGE_FW=y
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CONFIG_MTD_VIRT_CONCAT=y
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@ -88,6 +88,8 @@ CONFIG_GPIO_PCA953X=y
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CONFIG_GPIO_PCA953X_IRQ=y
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CONFIG_GPIO_REALTEK_OTTO=y
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CONFIG_GPIO_RTL8231=y
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CONFIG_GPIO_WATCHDOG=y
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# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
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CONFIG_GRO_CELLS=y
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CONFIG_HANDLE_DOMAIN_IRQ=y
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CONFIG_HARDWARE_WATCHPOINTS=y
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@ -150,6 +152,7 @@ CONFIG_MTD_SPI_NOR=y
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CONFIG_MTD_SPLIT_BRNIMAGE_FW=y
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CONFIG_MTD_SPLIT_EVA_FW=y
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CONFIG_MTD_SPLIT_FIRMWARE=y
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CONFIG_MTD_SPLIT_H3C_VFS=y
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CONFIG_MTD_SPLIT_TPLINK_FW=y
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CONFIG_MTD_SPLIT_UIMAGE_FW=y
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CONFIG_MTD_VIRT_CONCAT=y
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