rockchip: backport driver updates for rk3588
Backport upstreamed clk/mfd/phy/usb updates for rk3588. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/16149 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This commit is contained in:
Tianling Shen
Hauke Mehrtens
parent
c7c0b7bc02
commit
7108f5bd9f
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@ -0,0 +1,78 @@
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From 2dc66a5ab2c6fb532fbb16107ee7efcb0effbfa5 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Fri, 26 Jan 2024 19:18:22 +0100
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Subject: [PATCH] clk: rockchip: rk3588: fix CLK_NR_CLKS usage
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CLK_NR_CLKS is not part of the DT bindings and needs to be removed
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from it, just like it recently happened for other platforms. This
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takes care of it by introducing a new function identifying the
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maximum used clock ID at runtime.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20240126182919.48402-2-sebastian.reichel@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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drivers/clk/rockchip/clk-rk3588.c | 5 ++++-
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drivers/clk/rockchip/clk.c | 17 +++++++++++++++++
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drivers/clk/rockchip/clk.h | 2 ++
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3 files changed, 23 insertions(+), 1 deletion(-)
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--- a/drivers/clk/rockchip/clk-rk3588.c
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+++ b/drivers/clk/rockchip/clk-rk3588.c
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@@ -2458,15 +2458,18 @@ static struct rockchip_clk_branch rk3588
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static void __init rk3588_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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+ unsigned long clk_nr_clks;
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void __iomem *reg_base;
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+ clk_nr_clks = rockchip_clk_find_max_clk_id(rk3588_clk_branches,
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+ ARRAY_SIZE(rk3588_clk_branches)) + 1;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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pr_err("%s: could not map cru region\n", __func__);
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return;
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}
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- ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
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+ ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
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if (IS_ERR(ctx)) {
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pr_err("%s: rockchip clk init failed\n", __func__);
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iounmap(reg_base);
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--- a/drivers/clk/rockchip/clk.c
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+++ b/drivers/clk/rockchip/clk.c
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@@ -429,6 +429,23 @@ void rockchip_clk_register_plls(struct r
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}
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EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
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+unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
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+ unsigned int nr_clk)
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+{
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+ unsigned long max = 0;
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+ unsigned int idx;
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+
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+ for (idx = 0; idx < nr_clk; idx++, list++) {
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+ if (list->id > max)
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+ max = list->id;
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+ if (list->child && list->child->id > max)
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+ max = list->id;
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+ }
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+
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+ return max;
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+}
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+EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id);
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+
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void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
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struct rockchip_clk_branch *list,
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unsigned int nr_clk)
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--- a/drivers/clk/rockchip/clk.h
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+++ b/drivers/clk/rockchip/clk.h
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@@ -973,6 +973,8 @@ struct rockchip_clk_provider *rockchip_c
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void __iomem *base, unsigned long nr_clks);
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void rockchip_clk_of_add_provider(struct device_node *np,
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struct rockchip_clk_provider *ctx);
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+unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
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+ unsigned int nr_clk);
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void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
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struct rockchip_clk_branch *list,
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unsigned int nr_clk);
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@ -0,0 +1,27 @@
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From 11a29dc2e41ead2be78cfa9d532edf924b461acc Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Fri, 26 Jan 2024 19:18:23 +0100
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Subject: [PATCH] dt-bindings: clock: rk3588: drop CLK_NR_CLKS
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CLK_NR_CLKS should not be part of the binding. Let's drop it, since
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the kernel code no longer uses it either.
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20240126182919.48402-3-sebastian.reichel@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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include/dt-bindings/clock/rockchip,rk3588-cru.h | 2 --
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1 file changed, 2 deletions(-)
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--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h
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+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
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@@ -734,8 +734,6 @@
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#define PCLK_AV1_PRE 719
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#define HCLK_SDIO_PRE 720
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-#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1)
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-
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/* scmi-clocks indices */
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#define SCMI_CLK_CPUL 0
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@ -0,0 +1,26 @@
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From c81798cf9dd2f324934585b2b52a0398caefb88e Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Fri, 26 Jan 2024 19:18:24 +0100
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Subject: [PATCH] dt-bindings: clock: rk3588: add missing PCLK_VO1GRF
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Add PCLK_VO1GRF to complement PCLK_VO0GRF. This will be needed
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for HDMI support.
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Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20240126182919.48402-4-sebastian.reichel@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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include/dt-bindings/clock/rockchip,rk3588-cru.h | 1 +
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1 file changed, 1 insertion(+)
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--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h
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+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
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@@ -733,6 +733,7 @@
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#define ACLK_AV1_PRE 718
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#define PCLK_AV1_PRE 719
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#define HCLK_SDIO_PRE 720
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+#define PCLK_VO1GRF 721
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/* scmi-clocks indices */
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@ -0,0 +1,59 @@
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From 326be62eaf2e89767b7b9223f88eaf3c041b98d2 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Fri, 26 Jan 2024 19:18:25 +0100
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Subject: [PATCH] clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf
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Currently pclk_vo1grf is not exposed, but it should be referenced
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from the vo1_grf syscon, which needs it enabled. That syscon is
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required for HDMI RX and TX functionality among other things.
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Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates
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and need the VO's hclk enabled in addition to their parent clock.
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No Fixes tag has been added, since the logic requiring these clocks
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is not yet upstream anyways.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20240126182919.48402-5-sebastian.reichel@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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drivers/clk/rockchip/clk-rk3588.c | 10 ++++------
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1 file changed, 4 insertions(+), 6 deletions(-)
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--- a/drivers/clk/rockchip/clk-rk3588.c
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+++ b/drivers/clk/rockchip/clk-rk3588.c
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@@ -1851,8 +1851,6 @@ static struct rockchip_clk_branch rk3588
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RK3588_CLKGATE_CON(56), 0, GFLAGS),
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GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,
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RK3588_CLKGATE_CON(56), 1, GFLAGS),
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- GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED,
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- RK3588_CLKGATE_CON(55), 10, GFLAGS),
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COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0,
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RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,
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RK3588_CLKGATE_CON(56), 11, GFLAGS),
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@@ -1998,8 +1996,6 @@ static struct rockchip_clk_branch rk3588
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RK3588_CLKGATE_CON(60), 9, GFLAGS),
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GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,
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RK3588_CLKGATE_CON(60), 10, GFLAGS),
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- GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED,
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- RK3588_CLKGATE_CON(59), 12, GFLAGS),
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GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,
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RK3588_CLKGATE_CON(59), 14, GFLAGS),
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GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
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@@ -2447,12 +2443,14 @@ static struct rockchip_clk_branch rk3588
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GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
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GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
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GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
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- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS),
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+ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
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GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
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- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS),
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+ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
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GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
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GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
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GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
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+ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
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+ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
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};
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static void __init rk3588_clk_init(struct device_node *np)
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@ -0,0 +1,26 @@
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From 2a6e4710672242281347103b64e01693aa823a29 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Fri, 26 Jan 2024 19:18:26 +0100
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Subject: [PATCH] clk: rockchip: rk3588: fix indent
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pclk_mailbox2 is the only RK3588 clock indented with one tab instead of
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two tabs. Let's fix this.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20240126182919.48402-6-sebastian.reichel@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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drivers/clk/rockchip/clk-rk3588.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/clk/rockchip/clk-rk3588.c
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+++ b/drivers/clk/rockchip/clk-rk3588.c
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@@ -1004,7 +1004,7 @@ static struct rockchip_clk_branch rk3588
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GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0,
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RK3588_CLKGATE_CON(16), 12, GFLAGS),
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GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0,
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- RK3588_CLKGATE_CON(16), 13, GFLAGS),
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+ RK3588_CLKGATE_CON(16), 13, GFLAGS),
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GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL,
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RK3588_CLKGATE_CON(19), 3, GFLAGS),
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GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
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@ -0,0 +1,78 @@
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From dae3e57000fb2d6f491e3ee2956f5918326d6b72 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Fri, 26 Jan 2024 19:18:27 +0100
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Subject: [PATCH] clk: rockchip: rk3588: use linked clock ID for GATE_LINK
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In preparation for properly supporting GATE_LINK switch the unused
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linked clock argument from the clock's name to its ID. This allows
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easy and fast lookup of the 'struct clk'.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20240126182919.48402-7-sebastian.reichel@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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drivers/clk/rockchip/clk-rk3588.c | 46 +++++++++++++++----------------
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1 file changed, 23 insertions(+), 23 deletions(-)
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--- a/drivers/clk/rockchip/clk-rk3588.c
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+++ b/drivers/clk/rockchip/clk-rk3588.c
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@@ -29,7 +29,7 @@
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* power, but avoids leaking implementation details into DT or hanging the
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* system.
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*/
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-#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \
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+#define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
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GATE(_id, cname, pname, f, o, b, gf)
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#define RK3588_LINKED_CLK CLK_IS_CRITICAL
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@@ -2429,28 +2429,28 @@ static struct rockchip_clk_branch rk3588
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GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,
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RK3588_CLKGATE_CON(68), 2, GFLAGS),
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- GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
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- GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
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- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
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- GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
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- GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
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- GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
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- GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),
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- GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),
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- GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),
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- GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),
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- GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),
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- GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
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- GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
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- GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
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- GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
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- GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
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- GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
|
||||
- GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
|
||||
- GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
|
||||
- GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
|
||||
- GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
|
||||
- GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
|
||||
+ GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
|
||||
+ GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
|
||||
+ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
|
||||
+ GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
|
||||
+ GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
|
||||
+ GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
|
||||
+ GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),
|
||||
+ GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", ACLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),
|
||||
+ GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", HCLK_RKVENC0, 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),
|
||||
+ GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),
|
||||
+ GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),
|
||||
+ GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
|
||||
+ GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
|
||||
+ GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
|
||||
+ GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
|
||||
+ GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
|
||||
+ GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
|
||||
+ GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
|
||||
+ GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
|
||||
+ GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
|
||||
+ GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", HCLK_VO0, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
|
||||
+ GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
|
||||
};
|
||||
|
||||
static void __init rk3588_clk_init(struct device_node *np)
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
From ca151fd56b5736a7adbdba5675b9d87d70f20b23 Mon Sep 17 00:00:00 2001
|
||||
From: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Date: Thu, 28 Mar 2024 04:20:52 +0530
|
||||
Subject: [PATCH] dt-bindings: reset: Define reset id used for HDMI Receiver
|
||||
|
||||
Add reset id used for HDMI Receiver in RK3588 SoCs
|
||||
|
||||
Acked-by: Rob Herring <robh@kernel.org>
|
||||
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240327225057.672304-2-shreeya.patel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
include/dt-bindings/reset/rockchip,rk3588-cru.h | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/include/dt-bindings/reset/rockchip,rk3588-cru.h
|
||||
+++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
|
||||
@@ -751,4 +751,6 @@
|
||||
#define SRST_P_TRNG_CHK 658
|
||||
#define SRST_TRNG_S 659
|
||||
|
||||
+#define SRST_A_HDMIRX_BIU 660
|
||||
+
|
||||
#endif
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
From 7af67019cd78d028ef377df689ac103d51905518 Mon Sep 17 00:00:00 2001
|
||||
From: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Date: Thu, 28 Mar 2024 04:20:53 +0530
|
||||
Subject: [PATCH] clk: rockchip: rk3588: Add reset line for HDMI Receiver
|
||||
|
||||
Export hdmirx_biu reset line required by the Synopsys
|
||||
DesignWare HDMIRX Controller.
|
||||
|
||||
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240327225057.672304-3-shreeya.patel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/rst-rk3588.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/clk/rockchip/rst-rk3588.c
|
||||
+++ b/drivers/clk/rockchip/rst-rk3588.c
|
||||
@@ -577,6 +577,7 @@ static const int rk3588_register_offset[
|
||||
|
||||
/* SOFTRST_CON59 */
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6),
|
||||
+ RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX_BIU, 59, 7),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9),
|
||||
RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10),
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
From 2a46cd97f401a669d71b3d36b78bd6653f8424ee Mon Sep 17 00:00:00 2001
|
||||
From: Ondrej Jirman <megi@xff.cz>
|
||||
Date: Thu, 19 Oct 2023 18:57:25 +0200
|
||||
Subject: [PATCH] mfd: rk8xx: Add support for standard system-power-controller
|
||||
property
|
||||
|
||||
DT property rockchip,system-power-controller is now deprecated.
|
||||
|
||||
Signed-off-by: Ondrej Jirman <megi@xff.cz>
|
||||
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231019165732.3818789-4-megi@xff.cz
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
---
|
||||
drivers/mfd/rk8xx-core.c | 3 ++-
|
||||
1 file changed, 2 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/mfd/rk8xx-core.c
|
||||
+++ b/drivers/mfd/rk8xx-core.c
|
||||
@@ -677,7 +677,8 @@ int rk8xx_probe(struct device *dev, int
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to add MFD devices\n");
|
||||
|
||||
- if (device_property_read_bool(dev, "rockchip,system-power-controller")) {
|
||||
+ if (device_property_read_bool(dev, "rockchip,system-power-controller") ||
|
||||
+ device_property_read_bool(dev, "system-power-controller")) {
|
||||
ret = devm_register_sys_off_handler(dev,
|
||||
SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,
|
||||
&rk808_power_off, rk808);
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
From b0227e7081404448a0059b8698fdffd2dec280d2 Mon Sep 17 00:00:00 2001
|
||||
From: Ondrej Jirman <megi@xff.cz>
|
||||
Date: Thu, 19 Oct 2023 18:57:26 +0200
|
||||
Subject: [PATCH] mfd: rk8xx: Add support for RK806 power off
|
||||
|
||||
Use DEV_OFF bit to power off the RK806 PMIC, when system-power-controller
|
||||
is used in DTS.
|
||||
|
||||
Signed-off-by: Ondrej Jirman <megi@xff.cz>
|
||||
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231019165732.3818789-5-megi@xff.cz
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
---
|
||||
drivers/mfd/rk8xx-core.c | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
--- a/drivers/mfd/rk8xx-core.c
|
||||
+++ b/drivers/mfd/rk8xx-core.c
|
||||
@@ -517,6 +517,10 @@ static int rk808_power_off(struct sys_of
|
||||
reg = RK805_DEV_CTRL_REG;
|
||||
bit = DEV_OFF;
|
||||
break;
|
||||
+ case RK806_ID:
|
||||
+ reg = RK806_SYS_CFG3;
|
||||
+ bit = DEV_OFF;
|
||||
+ break;
|
||||
case RK808_ID:
|
||||
reg = RK808_DEVCTRL_REG,
|
||||
bit = DEV_OFF_RST;
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,35 @@
|
|||
From c9342d1a351ee1249fa98d936f756299a83d5684 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Tue, 16 Apr 2024 16:51:23 +0200
|
||||
Subject: [PATCH] phy: rockchip: usbdp: fix uninitialized variable
|
||||
|
||||
The ret variable may not be initialized in rk_udphy_usb3_phy_init(), if
|
||||
the PHY is not using USB3 mode.
|
||||
|
||||
Since the DisplayPort part is handled separately and the PHY does not
|
||||
support USB2 (which is routed to another PHY on Rockchip RK3588), the
|
||||
right exit code for this case is 0. Thus let's initialize the variable
|
||||
accordingly.
|
||||
|
||||
Fixes: 2f70bbddeb457 ("phy: rockchip: add usbdp combo phy driver")
|
||||
Reported-by: kernel test robot <lkp@intel.com>
|
||||
Closes: https://lore.kernel.org/oe-kbuild-all/202404141048.qFAYDctQ-lkp@intel.com/
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Reviewed-by: Muhammad Usama Anjum <usama.anjum@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240416145233.94687-1-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-usbdp.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
|
||||
@@ -1285,7 +1285,7 @@ static const struct phy_ops rk_udphy_dp_
|
||||
static int rk_udphy_usb3_phy_init(struct phy *phy)
|
||||
{
|
||||
struct rk_udphy *udphy = phy_get_drvdata(phy);
|
||||
- int ret;
|
||||
+ int ret = 0;
|
||||
|
||||
mutex_lock(&udphy->mutex);
|
||||
/* DP only or high-speed, disable U3 port */
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
From 9c79b779643e56d4253bd3ba6998c58c819943af Mon Sep 17 00:00:00 2001
|
||||
From: Arnd Bergmann <arnd@arndb.de>
|
||||
Date: Mon, 15 Apr 2024 19:42:25 +0200
|
||||
Subject: [PATCH] phy: rockchip: fix CONFIG_TYPEC dependency
|
||||
|
||||
The newly added driver causes a warning about missing dependencies
|
||||
by selecting CONFIG_TYPEC unconditionally:
|
||||
|
||||
WARNING: unmet direct dependencies detected for TYPEC
|
||||
Depends on [n]: USB_SUPPORT [=n]
|
||||
Selected by [y]:
|
||||
- PHY_ROCKCHIP_USBDP [=y] && ARCH_ROCKCHIP [=y] && OF [=y]
|
||||
|
||||
WARNING: unmet direct dependencies detected for USB_COMMON
|
||||
Depends on [n]: USB_SUPPORT [=n]
|
||||
Selected by [y]:
|
||||
- EXTCON_RTK_TYPE_C [=y] && EXTCON [=y] && (ARCH_REALTEK [=y] || COMPILE_TEST [=y]) && TYPEC [=y]
|
||||
|
||||
Since that is a user-visible option, it should not really be selected
|
||||
in the first place. Replace the 'select' with a 'depends on' as
|
||||
we have for similar drivers.
|
||||
|
||||
Fixes: 2f70bbddeb45 ("phy: rockchip: add usbdp combo phy driver")
|
||||
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://lore.kernel.org/r/20240415174241.77982-1-arnd@kernel.org
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/Kconfig | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/Kconfig
|
||||
+++ b/drivers/phy/rockchip/Kconfig
|
||||
@@ -111,8 +111,8 @@ config PHY_ROCKCHIP_USB
|
||||
config PHY_ROCKCHIP_USBDP
|
||||
tristate "Rockchip USBDP COMBO PHY Driver"
|
||||
depends on ARCH_ROCKCHIP && OF
|
||||
+ depends on TYPEC
|
||||
select GENERIC_PHY
|
||||
- select TYPEC
|
||||
help
|
||||
Enable this to support the Rockchip USB3.0/DP combo PHY with
|
||||
Samsung IP block. This is required for USB3 support on RK3588.
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
From 9b6bfad9070a95d19973be17177e5d9220cbbf1f Mon Sep 17 00:00:00 2001
|
||||
From: Rick Wertenbroek <rick.wertenbroek@gmail.com>
|
||||
Date: Thu, 7 Mar 2024 10:53:18 +0100
|
||||
Subject: [PATCH] phy: rockchip: Fix typo in function names
|
||||
|
||||
Several functions had "rochchip" instead of "rockchip" in their name.
|
||||
Replace "rochchip" by "rockchip".
|
||||
|
||||
Signed-off-By: Rick Wertenbroek <rick.wertenbroek@gmail.com>
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://lore.kernel.org/r/20240307095318.3651498-1-rick.wertenbroek@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 4 ++--
|
||||
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 12 ++++++------
|
||||
2 files changed, 8 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
||||
@@ -248,7 +248,7 @@ static int rockchip_combphy_exit(struct
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static const struct phy_ops rochchip_combphy_ops = {
|
||||
+static const struct phy_ops rockchip_combphy_ops = {
|
||||
.init = rockchip_combphy_init,
|
||||
.exit = rockchip_combphy_exit,
|
||||
.owner = THIS_MODULE,
|
||||
@@ -364,7 +364,7 @@ static int rockchip_combphy_probe(struct
|
||||
return ret;
|
||||
}
|
||||
|
||||
- priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
|
||||
+ priv->phy = devm_phy_create(dev, NULL, &rockchip_combphy_ops);
|
||||
if (IS_ERR(priv->phy)) {
|
||||
dev_err(dev, "failed to create combphy\n");
|
||||
return PTR_ERR(priv->phy);
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
@@ -182,7 +182,7 @@ static const struct rockchip_p3phy_ops r
|
||||
.phy_init = rockchip_p3phy_rk3588_init,
|
||||
};
|
||||
|
||||
-static int rochchip_p3phy_init(struct phy *phy)
|
||||
+static int rockchip_p3phy_init(struct phy *phy)
|
||||
{
|
||||
struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
int ret;
|
||||
@@ -205,7 +205,7 @@ static int rochchip_p3phy_init(struct ph
|
||||
return ret;
|
||||
}
|
||||
|
||||
-static int rochchip_p3phy_exit(struct phy *phy)
|
||||
+static int rockchip_p3phy_exit(struct phy *phy)
|
||||
{
|
||||
struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
|
||||
@@ -214,9 +214,9 @@ static int rochchip_p3phy_exit(struct ph
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static const struct phy_ops rochchip_p3phy_ops = {
|
||||
- .init = rochchip_p3phy_init,
|
||||
- .exit = rochchip_p3phy_exit,
|
||||
+static const struct phy_ops rockchip_p3phy_ops = {
|
||||
+ .init = rockchip_p3phy_init,
|
||||
+ .exit = rockchip_p3phy_exit,
|
||||
.set_mode = rockchip_p3phy_set_mode,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
@@ -275,7 +275,7 @@ static int rockchip_p3phy_probe(struct p
|
||||
return priv->num_lanes;
|
||||
}
|
||||
|
||||
- priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
|
||||
+ priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
|
||||
if (IS_ERR(priv->phy)) {
|
||||
dev_err(dev, "failed to create combphy\n");
|
||||
return PTR_ERR(priv->phy);
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
From a1fe1eca0d8be69ccc1f3d615e5a529df1c82e66 Mon Sep 17 00:00:00 2001
|
||||
From: Niklas Cassel <cassel@kernel.org>
|
||||
Date: Fri, 12 Apr 2024 14:58:16 +0200
|
||||
Subject: [PATCH] phy: rockchip-snps-pcie3: add support for
|
||||
rockchip,rx-common-refclk-mode
|
||||
|
||||
>From the RK3588 Technical Reference Manual, Part1,
|
||||
section 6.19 PCIe3PHY_GRF Register Description:
|
||||
"rxX_cmn_refclk_mode"
|
||||
RX common reference clock mode for lane X. This mode should be enabled
|
||||
only when the far-end and near-end devices are running with a common
|
||||
reference clock.
|
||||
|
||||
The hardware reset value for this field is 0x1 (enabled).
|
||||
Note that this register field is only available on RK3588, not on RK3568.
|
||||
|
||||
The link training either fails or is highly unstable (link state will jump
|
||||
continuously between L0 and recovery) when this mode is enabled while
|
||||
using an endpoint running in Separate Reference Clock with No SSC (SRNS)
|
||||
mode or Separate Reference Clock with SSC (SRIS) mode.
|
||||
(Which is usually the case when using a real SoC as endpoint, e.g. the
|
||||
RK3588 PCIe controller can run in both Root Complex and Endpoint mode.)
|
||||
|
||||
Add support for the device tree property rockchip,rx-common-refclk-mode,
|
||||
such that the PCIe PHY can be used in configurations where the Root
|
||||
Complex and Endpoint are not using a common reference clock.
|
||||
|
||||
Signed-off-by: Niklas Cassel <cassel@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20240412125818.17052-3-cassel@kernel.org
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
.../phy/rockchip/phy-rockchip-snps-pcie3.c | 37 +++++++++++++++++++
|
||||
1 file changed, 37 insertions(+)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
@@ -35,11 +35,17 @@
|
||||
#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
|
||||
#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
|
||||
#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
|
||||
+#define RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1 0x1004
|
||||
+#define RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1 0x1104
|
||||
+#define RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1 0x2004
|
||||
+#define RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1 0x2104
|
||||
#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
|
||||
|
||||
#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
|
||||
#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
|
||||
#define RK3588_LANE_AGGREGATION BIT(2)
|
||||
+#define RK3588_RX_CMN_REFCLK_MODE_EN ((BIT(7) << 16) | BIT(7))
|
||||
+#define RK3588_RX_CMN_REFCLK_MODE_DIS (BIT(7) << 16)
|
||||
#define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16)
|
||||
#define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16)
|
||||
|
||||
@@ -60,6 +66,7 @@ struct rockchip_p3phy_priv {
|
||||
int num_clks;
|
||||
int num_lanes;
|
||||
u32 lanes[4];
|
||||
+ u32 rx_cmn_refclk_mode[4];
|
||||
};
|
||||
|
||||
struct rockchip_p3phy_ops {
|
||||
@@ -137,6 +144,19 @@ static int rockchip_p3phy_rk3588_init(st
|
||||
u8 mode = RK3588_LANE_AGGREGATION; /* default */
|
||||
int ret;
|
||||
|
||||
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN0_CON1,
|
||||
+ priv->rx_cmn_refclk_mode[0] ? RK3588_RX_CMN_REFCLK_MODE_EN :
|
||||
+ RK3588_RX_CMN_REFCLK_MODE_DIS);
|
||||
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY0_LN1_CON1,
|
||||
+ priv->rx_cmn_refclk_mode[1] ? RK3588_RX_CMN_REFCLK_MODE_EN :
|
||||
+ RK3588_RX_CMN_REFCLK_MODE_DIS);
|
||||
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN0_CON1,
|
||||
+ priv->rx_cmn_refclk_mode[2] ? RK3588_RX_CMN_REFCLK_MODE_EN :
|
||||
+ RK3588_RX_CMN_REFCLK_MODE_DIS);
|
||||
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_PHY1_LN1_CON1,
|
||||
+ priv->rx_cmn_refclk_mode[3] ? RK3588_RX_CMN_REFCLK_MODE_EN :
|
||||
+ RK3588_RX_CMN_REFCLK_MODE_DIS);
|
||||
+
|
||||
/* Deassert PCIe PMA output clamp mode */
|
||||
regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));
|
||||
|
||||
@@ -275,6 +295,23 @@ static int rockchip_p3phy_probe(struct p
|
||||
return priv->num_lanes;
|
||||
}
|
||||
|
||||
+ ret = of_property_read_variable_u32_array(dev->of_node,
|
||||
+ "rockchip,rx-common-refclk-mode",
|
||||
+ priv->rx_cmn_refclk_mode, 1,
|
||||
+ ARRAY_SIZE(priv->rx_cmn_refclk_mode));
|
||||
+ /*
|
||||
+ * if no rockchip,rx-common-refclk-mode, assume enabled for all lanes in
|
||||
+ * order to be DT backwards compatible. (Since HW reset val is enabled.)
|
||||
+ */
|
||||
+ if (ret == -EINVAL) {
|
||||
+ for (int i = 0; i < ARRAY_SIZE(priv->rx_cmn_refclk_mode); i++)
|
||||
+ priv->rx_cmn_refclk_mode[i] = 1;
|
||||
+ } else if (ret < 0) {
|
||||
+ dev_err(dev, "failed to read rockchip,rx-common-refclk-mode property %d\n",
|
||||
+ ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
priv->phy = devm_phy_create(dev, NULL, &rockchip_p3phy_ops);
|
||||
if (IS_ERR(priv->phy)) {
|
||||
dev_err(dev, "failed to create combphy\n");
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
From 97789b93b792fc97ad4476b79e0f38ffa8e7e0ee Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Fri, 20 Oct 2023 16:11:41 +0200
|
||||
Subject: [PATCH] usb: dwc3: add optional PHY interface clocks
|
||||
|
||||
On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and
|
||||
requires two extra clocks to be enabled. Without these extra clocks
|
||||
hot-plugging USB devices is broken.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
|
||||
Link: https://lore.kernel.org/r/20231020150022.48725-3-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/usb/dwc3/core.c | 28 ++++++++++++++++++++++++++++
|
||||
drivers/usb/dwc3/core.h | 4 ++++
|
||||
2 files changed, 32 insertions(+)
|
||||
|
||||
--- a/drivers/usb/dwc3/core.c
|
||||
+++ b/drivers/usb/dwc3/core.c
|
||||
@@ -818,8 +818,20 @@ static int dwc3_clk_enable(struct dwc3 *
|
||||
if (ret)
|
||||
goto disable_ref_clk;
|
||||
|
||||
+ ret = clk_prepare_enable(dwc->utmi_clk);
|
||||
+ if (ret)
|
||||
+ goto disable_susp_clk;
|
||||
+
|
||||
+ ret = clk_prepare_enable(dwc->pipe_clk);
|
||||
+ if (ret)
|
||||
+ goto disable_utmi_clk;
|
||||
+
|
||||
return 0;
|
||||
|
||||
+disable_utmi_clk:
|
||||
+ clk_disable_unprepare(dwc->utmi_clk);
|
||||
+disable_susp_clk:
|
||||
+ clk_disable_unprepare(dwc->susp_clk);
|
||||
disable_ref_clk:
|
||||
clk_disable_unprepare(dwc->ref_clk);
|
||||
disable_bus_clk:
|
||||
@@ -829,6 +841,8 @@ disable_bus_clk:
|
||||
|
||||
static void dwc3_clk_disable(struct dwc3 *dwc)
|
||||
{
|
||||
+ clk_disable_unprepare(dwc->pipe_clk);
|
||||
+ clk_disable_unprepare(dwc->utmi_clk);
|
||||
clk_disable_unprepare(dwc->susp_clk);
|
||||
clk_disable_unprepare(dwc->ref_clk);
|
||||
clk_disable_unprepare(dwc->bus_clk);
|
||||
@@ -1842,6 +1856,20 @@ static int dwc3_get_clocks(struct dwc3 *
|
||||
}
|
||||
}
|
||||
|
||||
+ /* specific to Rockchip RK3588 */
|
||||
+ dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
|
||||
+ if (IS_ERR(dwc->utmi_clk)) {
|
||||
+ return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
|
||||
+ "could not get utmi clock\n");
|
||||
+ }
|
||||
+
|
||||
+ /* specific to Rockchip RK3588 */
|
||||
+ dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
|
||||
+ if (IS_ERR(dwc->pipe_clk)) {
|
||||
+ return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
|
||||
+ "could not get pipe clock\n");
|
||||
+ }
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
--- a/drivers/usb/dwc3/core.h
|
||||
+++ b/drivers/usb/dwc3/core.h
|
||||
@@ -996,6 +996,8 @@ struct dwc3_scratchpad_array {
|
||||
* @bus_clk: clock for accessing the registers
|
||||
* @ref_clk: reference clock
|
||||
* @susp_clk: clock used when the SS phy is in low power (S3) state
|
||||
+ * @utmi_clk: clock used for USB2 PHY communication
|
||||
+ * @pipe_clk: clock used for USB3 PHY communication
|
||||
* @reset: reset control
|
||||
* @regs: base address for our registers
|
||||
* @regs_size: address space size
|
||||
@@ -1166,6 +1168,8 @@ struct dwc3 {
|
||||
struct clk *bus_clk;
|
||||
struct clk *ref_clk;
|
||||
struct clk *susp_clk;
|
||||
+ struct clk *utmi_clk;
|
||||
+ struct clk *pipe_clk;
|
||||
|
||||
struct reset_control *reset;
|
||||
|
||||
Loading…
Reference in New Issue