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ar71xx: add preliminary support for the Atheros AR933x SoCs

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SVN-Revision: 27054
This commit is contained in:
Gabor Juhos 2011-05-31 22:53:26 +00:00
parent 761e67b394
commit 6b3ca9ef0b
5 changed files with 22 additions and 4 deletions
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1
target/linux/ar71xx/config-2.6.37
View File

@ -178,6 +178,7 @@ CONFIG_SLUB=y
CONFIG_SOC_AR71XX=y
CONFIG_SOC_AR724X=y
CONFIG_SOC_AR913X=y
# CONFIG_SOC_AR933X is not set
CONFIG_SOC_AR934X=y
CONFIG_SPI=y
CONFIG_SPI_AP83=y

1
target/linux/ar71xx/config-2.6.38
View File

@ -178,6 +178,7 @@ CONFIG_SLUB=y
CONFIG_SOC_AR71XX=y
CONFIG_SOC_AR724X=y
CONFIG_SOC_AR913X=y
# CONFIG_SOC_AR933X is not set
CONFIG_SOC_AR934X=y
CONFIG_SPI=y
CONFIG_SPI_AP83=y

4
target/linux/ar71xx/files/arch/mips/ar71xx/Kconfig
View File

@ -393,4 +393,8 @@ config AR71XX_NVRAM
config AR71XX_PCI_ATH9K_FIXUP
def_bool n
config SOC_AR933X
bool
select USB_ARCH_HAS_EHCI
endif

14
target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
View File

@ -143,10 +143,16 @@ static void __init ar71xx_detect_sys_type(void)
}
break;
case REV_ID_MAJOR_AR9341:
ar71xx_soc = AR71XX_SOC_AR9341;
chip = "9341";
rev = id & AR934X_REV_ID_REVISION_MASK;
case REV_ID_MAJOR_AR9330:
ar71xx_soc = AR71XX_SOC_AR9330;
chip = "9330";
rev = id & AR933X_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_AR9331:
ar71xx_soc = AR71XX_SOC_AR9331;
chip = "9331";
rev = id & AR933X_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_AR9342:

6
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
View File

@ -127,6 +127,8 @@ enum ar71xx_soc_type {
AR71XX_SOC_AR7242,
AR71XX_SOC_AR9130,
AR71XX_SOC_AR9132,
AR71XX_SOC_AR9330,
AR71XX_SOC_AR9331,
AR71XX_SOC_AR9341,
AR71XX_SOC_AR9342,
AR71XX_SOC_AR9344,
@ -641,6 +643,8 @@ void ar71xx_ddr_flush(u32 reg);
#define REV_ID_MAJOR_AR7240 0x00c0
#define REV_ID_MAJOR_AR7241 0x0100
#define REV_ID_MAJOR_AR7242 0x1100
#define REV_ID_MAJOR_AR9330 0x0110
#define REV_ID_MAJOR_AR9331 0x1110
#define REV_ID_MAJOR_AR9341 0x0120
#define REV_ID_MAJOR_AR9342 0x1120
#define REV_ID_MAJOR_AR9344 0x2120
@ -660,6 +664,8 @@ void ar71xx_ddr_flush(u32 reg);
#define AR724X_REV_ID_REVISION_MASK 0x3
#define AR933X_REV_ID_REVISION_MASK 0xf
#define AR934X_REV_ID_REVISION_MASK 0xf
extern void __iomem *ar71xx_reset_base;