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mediatek: fix PCIe #PERST being de-asserted too early

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The driver for MediaTek gen3 PCIe hosts de-asserts all reset
signals at the same time using a single register write operation.
Delay the de-assertion of the #PERST signal by 100ms as some PCIe
devices fail to come up otherwise.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle 2023-10-03 02:32:35 +01:00 committed by Christian Marangi
parent 32a696f9e4
commit 6a2e17d5c1
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GPG Key ID: AC001D09ADBFEAD7
3 changed files with 37 additions and 1 deletions
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17
target/linux/mediatek/patches-5.15/611-pcie-mediatek-gen3-PERST-for-100ms.patch Normal file
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@ -0,0 +1,17 @@
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -319,7 +319,13 @@ static int mtk_pcie_startup_port(struct
msleep(100);
/* De-assert reset signals */
- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
+ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
+ writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
+
+ msleep(100);
+
+ /* De-assert PERST# signals */
+ val &= ~(PCIE_PE_RSTB);
writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
/* Check if the link is up or not */

2
target/linux/mediatek/patches-5.15/922-v6.1-PCI-mediatek-gen3-change-driver-name-to-mtk-pcie-gen.patch
View File

@ -9,7 +9,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -1025,7 +1025,7 @@ static struct platform_driver mtk_pcie_d
@@ -1031,7 +1031,7 @@ static struct platform_driver mtk_pcie_d
.probe = mtk_pcie_probe,
.remove = mtk_pcie_remove,
.driver = {

19
target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch Normal file
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@ -0,0 +1,19 @@
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -350,9 +350,15 @@ static int mtk_pcie_startup_port(struct
msleep(100);
/* De-assert reset signals */
- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
+ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
+ msleep(100);
+
+ /* De-assert PERST# signals */
+ val &= ~(PCIE_PE_RSTB);
+ writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
+
/* Check if the link is up or not */
err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,
!!(val & PCIE_PORT_LINKUP), 20,