uboot-sunxi: various fixes - update A10-Lime support - fix MMC on sun5i with initializing PLL6 correctly
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> SVN-Revision: 39470
This commit is contained in:
Zoltan Herpai
parent
2ad7e55a89
commit
66543935db
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From 75ec90fda763b491e5169dcb6dce8abe3856d946 Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Sat, 14 Dec 2013 20:58:57 +0100
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Subject: [PATCH] sun5i: Give PLL6 a sane initial value
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The upstream kernel does not override PLL values as set by power-on-reset
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and/or the bootloader if it can avoid doing so.
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The power-on-reset value for PLL6 is 2400MHz, which does not actually work,
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the kernel does not know this and 2400 / 48 is 50 MHz, so the kernel happily
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tries to use it as is for mmc.
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Set PLL6 to a working frequency so that the kernel can use it. This fixes
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mmc in the upstream kernel not working on sun5i.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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arch/arm/cpu/armv7/sunxi/clock.c | 5 +++++
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1 file changed, 5 insertions(+)
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diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
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index 57b136d..b9dd608 100644
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--- a/arch/arm/cpu/armv7/sunxi/clock.c
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+++ b/arch/arm/cpu/armv7/sunxi/clock.c
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@@ -43,6 +43,11 @@ static void clock_init_safe(void)
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sdelay(200);
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writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 |
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CPU_CLK_SRC_PLL1 << 16, &ccm->cpu_ahb_apb0_cfg);
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+#ifdef CONFIG_SUN5I
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+ /* Power on reset default for PLL6 is 2400 MHz, which is faster then
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+ * it can reliable do :| Set it to a 600 MHz instead. */
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+ writel(0x21009900, &ccm->pll6_cfg);
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+#endif
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#ifdef CONFIG_SUN7I
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writel(0x1 << 6 | readl(&ccm->ahb_gate0), &ccm->ahb_gate0);
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writel(0x1 << 31 | readl(&ccm->pll6_cfg), &ccm->pll6_cfg);
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--
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1.8.5.1
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@ -0,0 +1,33 @@
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From 8f70a049daa30be894158411439a36f920f0d11c Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Wed, 15 Jan 2014 20:13:04 +0100
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Subject: [PATCH] sun5i: Tweak pll6 init value
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There are multiple ways to get 600 MHz from PLL6, the sun5i ccmu is very
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similar to the sun4i and sun7i ccmu.
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This commit changes the PLL6 initialization we do for sun5i to make the PLL6
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reg value match that of sun4i and sun7i. This also makes it closer to the
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sun5i power on default, as we are now only changing the K-factor from 3 to 1.
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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arch/arm/cpu/armv7/sunxi/clock.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
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index b9dd608..54b8753 100644
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--- a/arch/arm/cpu/armv7/sunxi/clock.c
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+++ b/arch/arm/cpu/armv7/sunxi/clock.c
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@@ -46,7 +46,7 @@ static void clock_init_safe(void)
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#ifdef CONFIG_SUN5I
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/* Power on reset default for PLL6 is 2400 MHz, which is faster then
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* it can reliable do :| Set it to a 600 MHz instead. */
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- writel(0x21009900, &ccm->pll6_cfg);
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+ writel(0x21009911, &ccm->pll6_cfg);
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#endif
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#ifdef CONFIG_SUN7I
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writel(0x1 << 6 | readl(&ccm->ahb_gate0), &ccm->ahb_gate0);
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--
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1.8.5.1
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@ -0,0 +1,94 @@
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From eccc92de2d133957fe2c126f18a5a5faef0bb93b Mon Sep 17 00:00:00 2001
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From: Hans de Goede <hdegoede@redhat.com>
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Date: Thu, 9 Jan 2014 23:26:05 +0100
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Subject: [PATCH] sunxi: A10-OLinuXino-Lime support fixup
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Fix:
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-code indentation
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-dram timings, the used cas and tpr0 - tpr2 were typical sun5i / sun7i
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settings, while they should be sun4i settings
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-Properly sort boards.cfg entry
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-Add status led support
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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---
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board/sunxi/dram_a10_olinuxino_l.c | 40 +++++++++++++++++++-------------------
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boards.cfg | 2 +-
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2 files changed, 21 insertions(+), 21 deletions(-)
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diff --git a/board/sunxi/dram_a10_olinuxino_l.c b/board/sunxi/dram_a10_olinuxino_l.c
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index 31b6542..24a1bd9 100644
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--- a/board/sunxi/dram_a10_olinuxino_l.c
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+++ b/board/sunxi/dram_a10_olinuxino_l.c
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@@ -4,28 +4,28 @@
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#include <asm/arch/dram.h>
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static struct dram_para dram_para = {
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- .clock = 480,
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- .type = 3,
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- .rank_num = 1,
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- .density = 4096,
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- .io_width = 16,
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- .bus_width = 16,
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- .cas = 9,
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- .zq = 123,
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- .odt_en = 0,
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- .size = 512,
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- .tpr0 = 0x42d899b7,
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- .tpr1 = 0xa090,
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- .tpr2 = 0x22a00,
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- .tpr3 = 0,
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- .tpr4 = 0,
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- .tpr5 = 0,
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- .emr1 = 0x4,
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- .emr2 = 0x10,
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- .emr3 = 0,
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+ .clock = 480,
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+ .type = 3,
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+ .rank_num = 1,
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+ .density = 4096,
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+ .io_width = 16,
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+ .bus_width = 16,
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+ .cas = 6,
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+ .zq = 123,
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+ .odt_en = 0,
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+ .size = 512,
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+ .tpr0 = 0x30926692,
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+ .tpr1 = 0x1090,
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+ .tpr2 = 0x1a0c8,
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+ .tpr3 = 0,
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+ .tpr4 = 0,
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+ .tpr5 = 0,
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+ .emr1 = 0x4,
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+ .emr2 = 0,
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+ .emr3 = 0,
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};
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unsigned long sunxi_dram_init(void)
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{
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- return dramc_init(&dram_para);
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+ return dramc_init(&dram_para);
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}
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diff --git a/boards.cfg b/boards.cfg
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index eda05de..dfeb07a 100644
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--- a/boards.cfg
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+++ b/boards.cfg
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@@ -345,6 +345,7 @@ Active arm armv7 s5pc1xx samsung goni
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Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
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Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
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Active arm armv7 sunxi - sunxi A10_MID_1GB sun4i:A10_MID_1GB,SPL -
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+Active arm armv7 sunxi - sunxi A10-OLinuXino-Lime sun4i:A10_OLINUXINO_L,STATUSLED=226,SPL,SUNXI_EMAC -
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Active arm armv7 sunxi - sunxi A10s-OLinuXino-M sun5i:A10S_OLINUXINO_M,STATUSLED=131,AXP152_POWER,CONS_INDEX=1,SPL,SUNXI_EMAC -
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Active arm armv7 sunxi - sunxi A10s-OLinuXino-M_FEL sun5i:A10S_OLINUXINO_M,STATUSLED=131,AXP152_POWER,CONS_INDEX=1,SPL_FEL,SUNXI_EMAC -
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Active arm armv7 sunxi - sunxi A13-OLinuXino sun5i:A13_OLINUXINO,SPL,STATUSLED=201,CONS_INDEX=2 -
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@@ -415,7 +416,6 @@ Active arm armv7 sunxi - sunxi
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Active arm armv7 sunxi - sunxi uhost_u1a sun4i:UHOST_U1A,SPL,STATUSLED=34 -
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Active arm armv7 sunxi - sunxi wobo-i5 sun5i:WOBO_I5,SPL,STATUSLED=34 -
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Active arm armv7 sunxi - sunxi xzpad700 sun5i:XZPAD700,SPL -
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-Active arm armv7 sunxi - sunxi A10-OLinuXino-Lime sun4i:A10_OLINUXINO_L,SPL,SUNXI_EMAC -
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Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
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Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
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Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
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--
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1.8.5.1
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