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imx: 6.6: add upstream patches for imx8m{m,n,p} venice

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Add a set of upstream patches for the imx8m{m,n,p} based Venice
boards.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Link: https://github.com/openwrt/openwrt/pull/15736
Signed-off-by: Robert Marko <robimarko@gmail.com>
This commit is contained in:
Tim Harvey 2024-05-21 12:18:50 -07:00 committed by Robert Marko
parent 176b8df701
commit 5f307b29cd
14 changed files with 717 additions and 0 deletions
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136
target/linux/imx/patches-6.6/400-6.7-arm64-dts-imx8mp-add-imx8mp-venice-gw74xx-imx219.patch Normal file
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@ -0,0 +1,136 @@
From 60fd951029603a0a6e019f16d53fb329dbd001f4 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Fri, 7 Jul 2023 16:24:19 -0700
Subject: [PATCH 400/413] 6.7: arm64: dts: imx8mp: add
imx8mp-venice-gw74xx-imx219 overlay for rpi v2 camera
Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module:
- https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf
- has its own on-board 24MHz osc so no clock required from baseboard
- pin 11 enables 1.8V and 2.8V LDO which is connected to
GW74xx MIPI_GPIO4 (IMX8MP GPIO1_IO4) so we use this as a gpio
Support is added via a device-tree overlay.
The IMX219 supports RAW8/RAW10 image formats.
Example configuration:
media-ctl -l "'imx219 3-0010':0->'csis-32e40000.csi':0[1]"
media-ctl -v -V "'imx219 3-0010':0 [fmt:SRGGB8/640x480 field:none]"
media-ctl -v -V "'crossbar':0 [fmt:SRGGB8/640x480 field:none]"
media-ctl -v -V "'mxc_isi.0':0 [fmt:SRGGB8/640x480 field:none]"
v4l2-ctl --set-fmt-video=width=640,height=480,pixelformat=RGGB
v4l2-ctl --stream-mmap --stream-to=frame.raw --stream-count=1
convert -size 640x480 -depth 8 gray:frame.raw frame.png
gst-launch-1.0 v4l2src ! \
video/x-bayer,format=rggb,width=640,height=480,framerate=10/1 ! \
bayer2rgb ! fbdevsink
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../imx8mp-venice-gw74xx-imx219.dtso | 80 +++++++++++++++++++
2 files changed, 82 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -159,6 +159,7 @@ imx8mm-venice-gw73xx-0x-rpidsi-dtbs := i
imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo
imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo
imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo
+imx8mp-venice-gw74xx-imx219-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-imx219.dtbo
imx8mp-venice-gw74xx-rpidsi-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-rpidsi.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtb
@@ -171,6 +172,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-imx219.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb
dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2023 Gateworks Corporation
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "imx8mp-pinfunc.h"
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "gw,imx8mp-gw74xx", "fsl,imx8mp";
+
+ reg_cam: regulator-cam {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_cam>;
+ compatible = "regulator-fixed";
+ regulator-name = "reg_cam";
+ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ cam24m: cam24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "cam24m";
+ };
+};
+
+&i2c4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imx219: sensor@10 {
+ compatible = "sony,imx219";
+ reg = <0x10>;
+ clocks = <&cam24m>;
+ VDIG-supply = <&reg_cam>;
+
+ port {
+ /* MIPI CSI-2 bus endpoint */
+ imx219_to_mipi_csi2: endpoint {
+ remote-endpoint = <&mipi_csi_0_in>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ link-frequencies = /bits/ 64 <456000000>;
+ };
+ };
+ };
+};
+
+&isi_0 {
+ status = "okay";
+};
+
+&mipi_csi_0 {
+ status = "okay";
+
+ ports {
+ port@0 {
+ mipi_csi_0_in: endpoint {
+ remote-endpoint = <&imx219_to_mipi_csi2>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_reg_cam: regcamgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x41
+ >;
+ };
+};

39
target/linux/imx/patches-6.6/401-6.7-arm64-dts-imx8mm-venice-gw73xx-add-TPM-device.patch Normal file
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@ -0,0 +1,39 @@
From 816e40232faaa4aa0364ca8da7f86eaf27b0d9ff Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Mon, 26 Jun 2023 11:51:13 -0700
Subject: [PATCH 401/413] 6.7: arm64: dts: imx8mm-venice-gw73xx: add TPM device
Add the TPM device found on the GW73xx revision F PCB.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
.../arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
@@ -104,8 +104,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio1 {
@@ -362,6 +369,7 @@
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
>;
};

39
target/linux/imx/patches-6.6/402-6.7-arm64-dts-imx8mp-venice-gw73xx-add-TPM-device.patch Normal file
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@ -0,0 +1,39 @@
From 916ffc08e8cdd3beccd78291eac9dc5592d83de1 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Thu, 24 Aug 2023 11:07:48 -0700
Subject: [PATCH 402/413] 6.7: arm64: dts: imx8mp-venice-gw73xx: add TPM device
Add the TPM device found on the GW73xx revision F PCB.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
.../arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
@@ -95,8 +95,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio4 {
@@ -327,6 +334,7 @@
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
>;
};

39
target/linux/imx/patches-6.6/403-6.8-arm64-dts-imx8mm-venice-gw72xx-add-TPM-device.patch Normal file
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@ -0,0 +1,39 @@
From 0adf19579692623d9d9202d2868aa7cd81451148 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Thu, 28 Sep 2023 14:10:39 -0700
Subject: [PATCH 403/413] 6.8: arm64: dts: imx8mm-venice-gw72xx: add TPM device
Add the TPM device found on the GW72xx revision F PCB.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
.../arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
@@ -84,8 +84,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio1 {
@@ -313,6 +320,7 @@
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
>;
};

39
target/linux/imx/patches-6.6/404-6.8-arm64-dts-imx8mp-venice-gw72xx-add-TPM-device.patch Normal file
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@ -0,0 +1,39 @@
From 9d3932717327f6086a9a81a41df5bf5250aee782 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Thu, 28 Sep 2023 14:11:01 -0700
Subject: [PATCH 404/413] 6.8: arm64: dts: imx8mp-venice-gw72xx: add TPM device
Add the TPM device found on the GW72xx revision F PCB.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
.../arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
@@ -83,8 +83,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio4 {
@@ -286,6 +293,7 @@
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
>;
};

39
target/linux/imx/patches-6.6/405-6.9-arm64-dts-imx8mm-venice-gw71xx-add-TPM-device.patch Normal file
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@ -0,0 +1,39 @@
From 6cea7c46172eca323e9ce7e6aab8f8506eb92b4b Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Wed, 29 Nov 2023 09:53:04 -0800
Subject: [PATCH 405/413] 6.9: arm64: dts: imx8mm-venice-gw71xx: add TPM device
Add the TPM device found on the GW71xx revision E PCB.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
.../arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
@@ -53,8 +53,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio1 {
@@ -201,6 +208,7 @@
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6
>;
};

39
target/linux/imx/patches-6.6/406-6.9-arm64-dts-imx8mp-venice-gw71xx-add-TPM-device.patch Normal file
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@ -0,0 +1,39 @@
From 9095a68c0b7084a7819e697ef38d0c987531c8ab Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Wed, 29 Nov 2023 17:11:51 -0800
Subject: [PATCH 406/413] 6.9: arm64: dts: imx8mp-venice-gw71xx: add TPM device
Add the TPM device found on the GW71xx revision E PCB.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
.../arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
@@ -48,8 +48,15 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
- cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
+ <&gpio1 10 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&gpio4 {
@@ -217,6 +224,7 @@
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
+ MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
>;
};

34
target/linux/imx/patches-6.6/407-6.9-arm64-dts-imx8mm-venice-gw7901-add-digital-I-O-d.patch Normal file
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@ -0,0 +1,34 @@
From e5bc89e60590581b0d31e8c6c6361c6caf5583bb Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 21 Nov 2023 11:12:24 -0800
Subject: [PATCH 407/413] 6.9: arm64: dts: imx8mm-venice-gw7901: add digital
I/O direction control GPIO's
The GW7901 has GPIO's to configure the direction of its isolated
digital I/O signals. Add the GPIO pinmux and line names.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
@@ -319,7 +319,7 @@
&gpio4 {
gpio-line-names = "", "", "", "",
- "", "", "uart3_rs232#", "uart3_rs422#",
+ "dig1_ctl", "dig2_ctl", "uart3_rs232#", "uart3_rs422#",
"uart3_rs485#", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
@@ -842,6 +842,8 @@
pinctrl_hog: hoggrp {
fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIG1_CTL */
+ MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000041 /* DIG2_CTL */
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */

45
target/linux/imx/patches-6.6/408-6.9-arm64-dts-imx8mm-venice-gw7901-add-TPM-device.patch Normal file
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@ -0,0 +1,45 @@
From f905e9a03cdf8edf6fa719ba89f37e6138c33834 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Tue, 21 Nov 2023 11:44:38 -0800
Subject: [PATCH 408/413] 6.9: arm64: dts: imx8mm-venice-gw7901: add TPM device
Add the TPM device found on the GW7901 revision D PCB.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
@@ -285,7 +285,8 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
- cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
+ <&gpio4 24 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 {
@@ -294,6 +295,12 @@
spi-max-frequency = <40000000>;
status = "okay";
};
+
+ tpm@1 {
+ compatible = "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ spi-max-frequency = <36000000>;
+ };
};
&fec1 {
@@ -989,6 +996,7 @@
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
+ MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140
>;
};

38
target/linux/imx/patches-6.6/409-6.9-arm64-dts-freescale-imx8mp-venice-gw72xx-2x-fix-.patch Normal file
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@ -0,0 +1,38 @@
From fddb089c2ccfb8bc4bd3aba605f7eadfd9f36cfd Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Wed, 28 Feb 2024 10:22:11 -0800
Subject: [PATCH 409/413] 6.9: arm64: dts: freescale: imx8mp-venice-gw72xx-2x:
fix USB vbus regulator
When using usb-conn-gpio to control USB role and VBUS, the vbus-supply
property must be present in the usb-conn-gpio node. Additionally it
should not be present in the phy node as that isn't what controls vbus
and will upset the use count.
This resolves an issue where VBUS is enabled with OTG in peripheral
mode.
Fixes: 86c43ae03ab9 ("arm64: dts: freescale: Add imx8mp-venice-gw72xx-2x")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
@@ -169,7 +169,6 @@
};
&usb3_phy0 {
- vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};
@@ -189,6 +188,7 @@
pinctrl-0 = <&pinctrl_usbcon1>;
type = "micro";
label = "otg";
+ vbus-supply = <&reg_usb1_vbus>;
id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
};
};

38
target/linux/imx/patches-6.6/410-6.9-arm64-dts-freescale-imx8mp-venice-gw73xx-2x-fix-.patch Normal file
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@ -0,0 +1,38 @@
From 69e3ce6d0c2f518bf9574112f3d4cc619c38602c Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Wed, 28 Feb 2024 10:24:19 -0800
Subject: [PATCH 410/413] 6.9: arm64: dts: freescale: imx8mp-venice-gw73xx-2x:
fix USB vbus regulator
When using usb-conn-gpio to control USB role and VBUS, the vbus-supply
property must be present in the usb-conn-gpio node. Additionally it
should not be present in the phy node as that isn't what controls vbus
and will upset the use count.
This resolves an issue where VBUS is enabled with OTG in peripheral
mode.
Fixes: 716ced308234 ("arm64: dts: freescale: Add imx8mp-venice-gw73xx-2x")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
@@ -188,7 +188,6 @@
};
&usb3_phy0 {
- vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};
@@ -208,6 +207,7 @@
pinctrl-0 = <&pinctrl_usbcon1>;
type = "micro";
label = "otg";
+ vbus-supply = <&reg_usb1_vbus>;
id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
};
};

30
target/linux/imx/patches-6.6/411-6.10-arm64-dts-imx8mp-venice-gw74xx-add-ADC-rail-for.patch Normal file
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@ -0,0 +1,30 @@
From 9d75bdd797d32c859d0dd9f54acc30de63831eb1 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Mon, 29 Jan 2024 15:28:39 -0800
Subject: [PATCH 411/413] 6.10: arm64: dts: imx8mp-venice-gw74xx: add ADC rail
for VDD_1P0
The imx8mp-venice-gw74xx revB PCB added an ADC rail for
VDD_1P0. Add it to the GSC ADC rails.
Fixes: 531936b218d8 ("arm64: dts: imx8mp-venice-gw74xx: update to revB PCB")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
@@ -391,6 +391,12 @@
label = "vdd_dram";
};
+ channel@9e {
+ gw,mode = <2>;
+ reg = <0x9e>;
+ label = "vdd_1p0";
+ };
+
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;

80
target/linux/imx/patches-6.6/412-6.10-arm64-dts-imx8mp-venice-gw72xx-add-mac-addr-for.patch Normal file
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@ -0,0 +1,80 @@
From 482fe0cb90d3376051304531a01edccac9ca1868 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Thu, 29 Feb 2024 10:05:26 -0800
Subject: [PATCH 412/413] 6.10: arm64: dts: imx8mp-venice-gw72xx: add mac addr
for eth1
Add the PCI bus topology for eth1 so that boot firmware can set the
local-mac-address property.
The eth1 device is behind a PCI switch:
# lspci -n
00:00.0 0604: 16c3:abcd (rev 01)
01:00.0 0604: 12d8:b404 (rev 01)
02:01.0 0604: 12d8:b404 (rev 01)
02:02.0 0604: 12d8:b404 (rev 01)
02:03.0 0604: 12d8:b404 (rev 01)
05:00.0 0200: 11ab:4380
# lspci -t
-[0000:00]---00.0-[01-ff]----00.0-[02-05]--+-01.0-[03]--
+-02.0-[04]--
\-03.0-[05]----00.0
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
.../dts/freescale/imx8mp-venice-gw72xx.dtsi | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
@@ -8,6 +8,10 @@
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
+ aliases {
+ ethernet1 = &eth1;
+ };
+
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -137,6 +141,39 @@
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ pcie@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ pcie@3,0 {
+ reg = <0x1800 0 0 0 0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ eth1: ethernet@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
+ };
};
/* GPS */

82
target/linux/imx/patches-6.6/413-6.10-arm64-dts-imx8mp-venice-gw73xx-add-mac-addr-for.patch Normal file
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@ -0,0 +1,82 @@
From caac9b614ee63f875b290fda429706f6ef36e2f1 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Thu, 29 Feb 2024 10:12:49 -0800
Subject: [PATCH 413/413] 6.10: arm64: dts: imx8mp-venice-gw73xx: add mac addr
for eth1
Add the PCI bus topology for eth1 so that boot firmware can set the
local-mac-address property.
The eth1 device is behind a PCI switch:
# lspci -n
00:00.0 0604: 16c3:abcd (rev 01)
01:00.0 0604: 12d8:2608
02:01.0 0604: 12d8:2608
02:02.0 0604: 12d8:2608
02:03.0 0604: 12d8:2608
02:04.0 0604: 12d8:2608
c0:00.0 0200: 1055:7430 (rev 11)
# lspci -t
-[0000:00]---00.0-[01-ff]----00.0-[02-fe]--+-01.0-[03-41]--
+-02.0-[42-80]--
+-03.0-[81-bf]--
\-04.0-[c0-fe]----00.0
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
.../dts/freescale/imx8mp-venice-gw73xx.dtsi | 37 +++++++++++++++++++
1 file changed, 37 insertions(+)
--- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
@@ -8,6 +8,10 @@
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
+ aliases {
+ ethernet1 = &eth1;
+ };
+
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -149,6 +153,39 @@
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ pcie@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ pcie@4,0 {
+ reg = <0x2000 0 0 0 0>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ eth1: ethernet@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ local-mac-address = [00 00 00 00 00 00];
+ };
+ };
+ };
+ };
};
/* GPS */