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ar71xx: fix DDR write buffer flushing issues with 4.4 

Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Felix Fietkau 2016-05-14 20:24:37 +02:00
parent e30608b736
commit 5b34dffcbd
13 changed files with 1388 additions and 99 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1315
target/linux/ar71xx/files-4.1/arch/mips/ath79/dev-eth.c Normal file
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File diff suppressed because it is too large Load Diff

93
target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
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@ -407,48 +407,14 @@ static void ath79_set_speed_dummy(int speed)
{
}
static void ath79_ddr_no_flush(void)
{
}
static void ath79_ddr_flush_ge0(void)
{
ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
ath79_ddr_wb_flush(0);
}
static void ath79_ddr_flush_ge1(void)
{
ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
}
static void ar724x_ddr_flush_ge0(void)
{
ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
}
static void ar724x_ddr_flush_ge1(void)
{
ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
}
static void ar91xx_ddr_flush_ge0(void)
{
ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
}
static void ar91xx_ddr_flush_ge1(void)
{
ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
}
static void ar933x_ddr_flush_ge0(void)
{
ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
}
static void ar933x_ddr_flush_ge1(void)
{
ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
ath79_ddr_wb_flush(1);
}
static struct resource ath79_eth0_resources[] = {
@ -879,26 +845,25 @@ void __init ath79_register_eth(unsigned int id)
return;
}
if (id == 0)
pdata->ddr_flush = ath79_ddr_flush_ge0;
else
pdata->ddr_flush = ath79_ddr_flush_ge1;
switch (ath79_soc) {
case ATH79_SOC_AR7130:
if (id == 0) {
pdata->ddr_flush = ath79_ddr_flush_ge0;
if (id == 0)
pdata->set_speed = ath79_set_speed_ge0;
} else {
pdata->ddr_flush = ath79_ddr_flush_ge1;
else
pdata->set_speed = ath79_set_speed_ge1;
}
break;
case ATH79_SOC_AR7141:
case ATH79_SOC_AR7161:
if (id == 0) {
pdata->ddr_flush = ath79_ddr_flush_ge0;
if (id == 0)
pdata->set_speed = ath79_set_speed_ge0;
} else {
pdata->ddr_flush = ath79_ddr_flush_ge1;
else
pdata->set_speed = ath79_set_speed_ge1;
}
pdata->has_gbit = 1;
break;
@ -906,12 +871,10 @@ void __init ath79_register_eth(unsigned int id)
if (id == 0) {
pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
AR71XX_RESET_GE0_PHY;
pdata->ddr_flush = ar724x_ddr_flush_ge0;
pdata->set_speed = ar7242_set_speed_ge0;
} else {
pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
AR71XX_RESET_GE1_PHY;
pdata->ddr_flush = ar724x_ddr_flush_ge1;
pdata->set_speed = ath79_set_speed_dummy;
}
pdata->has_gbit = 1;
@ -934,13 +897,11 @@ void __init ath79_register_eth(unsigned int id)
case ATH79_SOC_AR7240:
if (id == 0) {
pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
pdata->ddr_flush = ar724x_ddr_flush_ge0;
pdata->set_speed = ath79_set_speed_dummy;
pdata->phy_mask = BIT(4);
} else {
pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
pdata->ddr_flush = ar724x_ddr_flush_ge1;
pdata->set_speed = ath79_set_speed_dummy;
pdata->speed = SPEED_1000;
@ -962,27 +923,15 @@ void __init ath79_register_eth(unsigned int id)
pdata->fifo_cfg3 = 0x01f00140;
break;
case ATH79_SOC_AR9130:
if (id == 0) {
pdata->ddr_flush = ar91xx_ddr_flush_ge0;
pdata->set_speed = ar91xx_set_speed_ge0;
} else {
pdata->ddr_flush = ar91xx_ddr_flush_ge1;
pdata->set_speed = ar91xx_set_speed_ge1;
}
pdata->is_ar91xx = 1;
break;
case ATH79_SOC_AR9132:
if (id == 0) {
pdata->ddr_flush = ar91xx_ddr_flush_ge0;
pdata->set_speed = ar91xx_set_speed_ge0;
} else {
pdata->ddr_flush = ar91xx_ddr_flush_ge1;
pdata->set_speed = ar91xx_set_speed_ge1;
}
pdata->is_ar91xx = 1;
pdata->has_gbit = 1;
/* fall through */
case ATH79_SOC_AR9130:
if (id == 0)
pdata->set_speed = ar91xx_set_speed_ge0;
else
pdata->set_speed = ar91xx_set_speed_ge1;
pdata->is_ar91xx = 1;
break;
case ATH79_SOC_AR9330:
@ -990,14 +939,12 @@ void __init ath79_register_eth(unsigned int id)
if (id == 0) {
pdata->reset_bit = AR933X_RESET_GE0_MAC |
AR933X_RESET_GE0_MDIO;
pdata->ddr_flush = ar933x_ddr_flush_ge0;
pdata->set_speed = ath79_set_speed_dummy;
pdata->phy_mask = BIT(4);
} else {
pdata->reset_bit = AR933X_RESET_GE1_MAC |
AR933X_RESET_GE1_MDIO;
pdata->ddr_flush = ar933x_ddr_flush_ge1;
pdata->set_speed = ath79_set_speed_dummy;
pdata->speed = SPEED_1000;
@ -1038,7 +985,6 @@ void __init ath79_register_eth(unsigned int id)
ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
}
pdata->ddr_flush = ath79_ddr_no_flush;
pdata->has_gbit = 1;
pdata->is_ar724x = 1;
@ -1073,7 +1019,6 @@ void __init ath79_register_eth(unsigned int id)
ath79_switch_data.phy_poll_mask |= BIT(4);
}
pdata->ddr_flush = ath79_ddr_no_flush;
pdata->has_gbit = 1;
pdata->is_ar724x = 1;
@ -1097,7 +1042,6 @@ void __init ath79_register_eth(unsigned int id)
pdata->set_speed = qca955x_set_speed_sgmii;
}
pdata->ddr_flush = ath79_ddr_no_flush;
pdata->has_gbit = 1;
pdata->is_ar724x = 1;
@ -1145,7 +1089,6 @@ void __init ath79_register_eth(unsigned int id)
ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
}
pdata->ddr_flush = ath79_ddr_no_flush;
pdata->has_gbit = 1;
pdata->is_ar724x = 1;

31
target/linux/ar71xx/patches-4.4/101-MIPS-ath79-make-ath79_ddr_ctrl_init-compatible-for-n.patch Normal file
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@ -0,0 +1,31 @@
From: Felix Fietkau <nbd@nbd.name>
Date: Sat, 14 May 2016 20:20:04 +0200
Subject: [PATCH] MIPS: ath79: make ath79_ddr_ctrl_init() compatible for newer
SoCs
AR913x, AR724x and AR933x are the only SoCs where the
ath79_ddr_wb_flush_base starts at 0x7c, all newer SoCs use 0x9c
Invert the logic to make the code compatible with AR95xx
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
@@ -46,12 +46,12 @@ void ath79_ddr_ctrl_init(void)
{
ath79_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
AR71XX_DDR_CTRL_SIZE);
- if (soc_is_ar71xx() || soc_is_ar934x()) {
- ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
- ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
- } else {
+ if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) {
ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
ath79_ddr_pci_win_base = 0;
+ } else {
+ ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
+ ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
}
}
EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);

2
target/linux/ar71xx/patches-4.4/407-mtd-m25p80-allow-to-pass-probe-types-via-platform-data.patch
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@ -1,6 +1,6 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -229,7 +229,9 @@ static int m25p_probe(struct spi_device
@@ -251,7 +251,9 @@ static int m25p_probe(struct spi_device
ppdata.of_node = spi->dev.of_node;

2
target/linux/ar71xx/patches-4.4/412-mtd-m25p80-zero-partition-parser-data.patch
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@ -1,6 +1,6 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -227,6 +227,7 @@ static int m25p_probe(struct spi_device
@@ -249,6 +249,7 @@ static int m25p_probe(struct spi_device
if (ret)
return ret;

4
target/linux/ar71xx/patches-4.4/431-spi-add-various-flags.patch
View File

@ -1,6 +1,6 @@
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -690,6 +690,8 @@ struct spi_transfer {
@@ -695,6 +695,8 @@ struct spi_transfer {
unsigned cs_change:1;
unsigned tx_nbits:3;
unsigned rx_nbits:3;
@ -9,7 +9,7 @@
#define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
#define SPI_NBITS_DUAL 0x02 /* 2bits transfer */
#define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
@@ -735,6 +737,7 @@ struct spi_message {
@@ -740,6 +742,7 @@ struct spi_message {
struct spi_device *spi;
unsigned is_dma_mapped:1;

4
target/linux/ar71xx/patches-4.4/461-spi-add-type-field-to-spi_transfer.patch
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@ -1,6 +1,6 @@
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -578,6 +578,12 @@ extern struct spi_master *spi_busnum_to_
@@ -583,6 +583,12 @@ extern struct spi_master *spi_busnum_to_
/*---------------------------------------------------------------------------*/
@ -13,7 +13,7 @@
/*
* I/O INTERFACE between SPI controller and protocol drivers
*
@@ -698,6 +704,7 @@ struct spi_transfer {
@@ -703,6 +709,7 @@ struct spi_transfer {
u8 bits_per_word;
u16 delay_usecs;
u32 speed_hz;

2
target/linux/ar71xx/patches-4.4/462-mtd-m25p80-set-spi-transfer-type.patch
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@ -1,6 +1,6 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -137,10 +137,12 @@ static int m25p80_read(struct spi_nor *n
@@ -159,10 +159,12 @@ static int m25p80_read(struct spi_nor *n
flash->command[0] = nor->read_opcode;
m25p_addr2cmd(nor, from, flash->command);

4
target/linux/ar71xx/patches-4.4/464-spi-ath79-fix-fast-flash-read.patch
View File

@ -1,6 +1,6 @@
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -137,6 +137,9 @@ static int m25p80_read(struct spi_nor *n
@@ -159,6 +159,9 @@ static int m25p80_read(struct spi_nor *n
flash->command[0] = nor->read_opcode;
m25p_addr2cmd(nor, from, flash->command);
@ -25,7 +25,7 @@
while (len--) {
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -705,6 +705,7 @@ struct spi_transfer {
@@ -710,6 +710,7 @@ struct spi_transfer {
u16 delay_usecs;
u32 speed_hz;
enum spi_transfer_type type;

8
target/linux/ar71xx/patches-4.4/525-MIPS-ath79-enable-qca-usb-quirks.patch
View File

@ -29,7 +29,9 @@
- u32 bootstrap;
+ void __iomem *phy_reg;
+ u32 t;
+
- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
+ phy_reg = ioremap(base, 4);
+ if (!phy_reg)
+ return;
@ -41,9 +43,7 @@
+
+ iounmap(phy_reg);
+}
- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
+
+static void ar934x_usb_reset_notifier(struct platform_device *pdev)
+{
+ if (pdev->id != -1)

4
target/linux/ar71xx/patches-4.4/601-MIPS-ath79-add-more-register-defines.patch
View File

@ -155,7 +155,7 @@
+#define AR934X_RESET_LUT BIT(2)
+#define AR934X_RESET_MBOX BIT(1)
+#define AR934X_RESET_I2S BIT(0)
+
+#define QCA955X_RESET_HOST BIT(31)
+#define QCA955X_RESET_SLIC BIT(30)
+#define QCA955X_RESET_HDMA BIT(29)
@ -188,7 +188,7 @@
+#define QCA955X_RESET_LUT BIT(2)
+#define QCA955X_RESET_MBOX BIT(1)
+#define QCA955X_RESET_I2S BIT(0)
+
+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)

14
target/linux/ar71xx/patches-4.4/609-MIPS-ath79-ap136-fixes.patch
View File

@ -135,7 +135,8 @@
+static void __init ap136_common_setup(void)
+{
+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+
-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
+ ath79_register_m25p80(NULL);
+
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
@ -150,8 +151,7 @@
+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
+
+ ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
+
+ ath79_register_mdio(0, 0x0);
+ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
+
@ -211,16 +211,16 @@
+ /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
+ ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
+ ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
+
- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
- ath79_register_pci();
+ /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
+ ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
+ ap136_ar8327_pad6_cfg.txclk_delay_en = true;
+ ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
+ ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
+ ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
- ath79_register_pci();
+
+ ath79_eth0_pll_data.pll_1000 = 0x56000000;
+ ath79_eth1_pll_data.pll_1000 = 0x03000101;
+

4
target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
View File

@ -335,10 +335,10 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
+ status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
+
+ if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
+ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_PCIE);
+ ath79_ddr_wb_flush(3);
+ generic_handle_irq(ATH79_IP2_IRQ(0));
+ } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
+ ath79_ddr_wb_flush(QCA953X_DDR_REG_FLUSH_WMAC);
+ ath79_ddr_wb_flush(4);
+ generic_handle_irq(ATH79_IP2_IRQ(1));
+ } else {
+ spurious_interrupt();