From 533235182141392d8031a6d2edb9d7edc91bfd5a Mon Sep 17 00:00:00 2001 From: David Bauer Date: Fri, 27 Sep 2024 19:10:40 +0200 Subject: [PATCH] ipq40xx: fix AP-303H PSE GPIO pin The GPIO chip is at a different start index compared to OpenWrt master. Signed-off-by: David Bauer --- target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches b/target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches index f57d4c5888..fcc6e8e745 100644 --- a/target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches +++ b/target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches @@ -7,7 +7,7 @@ board=$(board_name) case "$board" in aruba,ap-303h) - ucidef_add_gpio_switch "poe_passtrough" "POE passtrough disable" "546" "1" + ucidef_add_gpio_switch "poe_passtrough" "POE passtrough disable" "446" "1" ;; cellc,rtl30vw) ucidef_add_gpio_switch "w_disable" "W_DISABLE mPCIE pin" "398" "1"