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uboot-mvebu: update to version v2022.04
Release announcement: https://lore.kernel.org/u-boot/20220404143253.GQ14476@bill-the-cat/ Release notes between tags: https://source.denx.de/u-boot/u-boot/-/compare/v2022.01...v2022.04?from_project_id=531 All patches were removed, since they are included in this release. Run tested: Turris Omnia, mvebu/cortex-a9, OpenWrt daily snapshots Signed-off-by: Josef Schlehofer <pepe.schlehofer@gmail.com>
This commit is contained in:
Josef Schlehofer
Hauke Mehrtens
parent
69cef74c67
commit
4f51f1fc9b
@ -8,10 +8,10 @@
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include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/kernel.mk
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PKG_VERSION:=2022.01
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PKG_VERSION:=2022.04
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PKG_RELEASE:=$(AUTORELEASE)
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PKG_HASH:=81b4543227db228c03f8a1bf5ddbc813b0bb8f6555ce46064ef721a6fc680413
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PKG_HASH:=68e065413926778e276ec3abd28bb32fa82abaa4a6898d570c1f48fbdb08bcd0
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include $(INCLUDE_DIR)/u-boot.mk
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include $(INCLUDE_DIR)/package.mk
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@ -1,116 +0,0 @@
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From 3fc92a215b69ad448c151489228eb340df9a8703 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
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Date: Wed, 12 Jan 2022 17:06:59 +0100
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Subject: [PATCH] ddr: marvell: a38x: fix SPLIT_OUT_MIX state decision
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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This is a cleaned up and fixed version of a patch
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mv_ddr: a380: fix SPLIT_OUT_MIX state decision
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in each pattern cycle the bus state can be changed
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in order to avoide it, need to back to the same bus state on each
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pattern cycle
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by
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Moti Boskula <motib@marvell.com>
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The original patch is not in Marvell's mv-ddr-marvell repository. It was
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gives to us by Marvell to fix an issues with DDR training on some
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boards, but it cannot be applied as is to mv-ddr-marvell, because it is
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a very dirty draft patch that would certainly break other things, mainly
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DDR4 training code in mv-ddr-marvell, since it changes common functions.
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I have cleaned up the patch and removed stuff that seemed unnecessary
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(when removed, it still fixed things). Note that I don't understand
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completely what the code does exactly, since I haven't studied the DDR
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training code extensively (and I suspect that no one besides some few
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people in Marvell understand the code completely).
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Anyway after the cleanup the patch still fixes isssues with DDR training
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on the failing boards.
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There was also a problem with the original patch on some of the Allied
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Telesis' x530 boards, reported by Chris Packham. I have asked Chris to
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send me some logs, and managed to fix it:
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- if you look at the change, you'll notice that it introduces
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subtraction of cur_start_win[] and cur_end_win[] members, depending on
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a bit set in the current_byte_status variable
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- the original patch subtracted cur_start_win[] if either
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BYTE_SPLIT_OUT_MIX or BYTE_HOMOGENEOUS_SPLIT_OUT bits were set, but
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subtracted cur_end_win[] only if the first one (BYTE_SPLIT_OUT_MIX)
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was set
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- from Chris Packham logs I discovered that the x530 board where the
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original patch introduced DDR training failure, only the
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BYTE_HOMOGENEOUS_SPLIT_OUT bit was set, and on our boards where the
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patch is needed only the BYTE_SPLIT_OUT_MIX is set in the
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current_byte_status variable
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- this led me to the hypothesis that both cur_start_win[] and
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cur_end_win[] should be subtracted only if BYTE_SPLIT_OUT_MIX bit is
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set, the BYTE_HOMOGENEOUS_SPLIT_OUT bit shouldn't be considered at all
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- this hypothesis also gains credibility when considering the commit
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title ("fix SPLIT_OUT_MIX state decision")
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Hopefully this will fix things without breaking anything else.
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Signed-off-by: Marek Behún <marek.behun@nic.cz>
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Reviewed-by: Stefan Roese <sr@denx.de>
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Tested-by: Chris Packham <judge.packham@gmail.com>
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---
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.../a38x/ddr3_training_centralization.c | 26 +++++++++++++++++++
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1 file changed, 26 insertions(+)
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--- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
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+++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
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@@ -55,6 +55,7 @@ static int ddr3_tip_centralization(u32 d
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enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM];
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u32 if_id, pattern_id, bit_id;
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u8 bus_id;
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+ u8 current_byte_status;
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u8 cur_start_win[BUS_WIDTH_IN_BITS];
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u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS];
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u8 cur_end_win[BUS_WIDTH_IN_BITS];
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@@ -166,6 +167,10 @@ static int ddr3_tip_centralization(u32 d
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result[search_dir_id][7]));
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}
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+ current_byte_status =
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+ mv_ddr_tip_sub_phy_byte_status_get(if_id,
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+ bus_id);
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+
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for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS;
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bit_id++) {
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/* check if this code is valid for 2 edge, probably not :( */
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@@ -174,11 +179,32 @@ static int ddr3_tip_centralization(u32 d
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[HWS_LOW2HIGH]
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[bit_id],
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EDGE_1);
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+ if (current_byte_status &
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+ BYTE_SPLIT_OUT_MIX) {
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+ if (cur_start_win[bit_id] >= 64)
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+ cur_start_win[bit_id] -= 64;
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+ else
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+ cur_start_win[bit_id] = 0;
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+ DEBUG_CENTRALIZATION_ENGINE
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+ (DEBUG_LEVEL_INFO,
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+ ("pattern %d IF %d pup %d bit %d subtract 64 adll from start\n",
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+ pattern_id, if_id, bus_id, bit_id));
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+ }
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cur_end_win[bit_id] =
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GET_TAP_RESULT(result
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[HWS_HIGH2LOW]
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[bit_id],
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EDGE_1);
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+ if (cur_end_win[bit_id] >= 64 &&
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+ (current_byte_status &
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+ BYTE_SPLIT_OUT_MIX)) {
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+ cur_end_win[bit_id] -= 64;
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+ DEBUG_CENTRALIZATION_ENGINE
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+ (DEBUG_LEVEL_INFO,
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+ ("pattern %d IF %d pup %d bit %d subtract 64 adll from end\n",
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+ pattern_id, if_id, bus_id, bit_id));
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+ }
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+
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/* window length */
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current_window[bit_id] =
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cur_end_win[bit_id] -
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@ -1,98 +0,0 @@
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From eadc4f512fb43bba2fa4e842c982da919da664be Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
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Date: Tue, 4 Jan 2022 15:57:49 +0100
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Subject: [PATCH] ddr: marvell: a38x: Fix Synchronous vs Asynchronous mode
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determination
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Before commit 4c289425752f ("mv_ddr: a38x: add support for ddr async
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mode"), Asynchornous Mode was only used when the CPU Subsystem Clock
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Options[4:0] field in the SAR1 register was set to value 0x13: CPU at
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2 GHz and DDR at 933 MHz.
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Then commit 4c289425752f ("mv_ddr: a38x: add support for ddr async
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mode") added support for Asynchornous Modes with frequencies other than
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933 MHz (but at least 467 MHz), but the code it added to check for
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whether Asynchornous Mode should be used is wrong: it checks whether the
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frequency setting in board DDR topology map is set to value other than
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MV_DDR_FREQ_SAR.
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Thus boards which define a specific value, greater than 400 MHz, for DDR
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frequency in their board topology (e.g. Turris Omnia defines
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MV_DDR_FREQ_800), are incorrectly put into Asynchornous Mode after that
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commit.
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The A38x Functional Specification, section 10.12 DRAM Clocking, says:
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In Synchornous mode, the DRAM and CPU clocks are edge aligned and run
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in 1:2 or 1:3 CPU to DRAM frequency ratios.
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Change the check for whether Asynchornous Mode should be used according
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to this explanation in Functional Specification.
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Signed-off-by: Marek Behún <marek.behun@nic.cz>
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Tested-by: Chris Packham <judge.packham@gmail.com>
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Reviewed-by: Stefan Roese <sr@denx.de>
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---
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drivers/ddr/marvell/a38x/mv_ddr_plat.c | 19 ++++++++-----------
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1 file changed, 8 insertions(+), 11 deletions(-)
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--- a/drivers/ddr/marvell/a38x/mv_ddr_plat.c
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+++ b/drivers/ddr/marvell/a38x/mv_ddr_plat.c
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@@ -167,8 +167,6 @@ static u16 a38x_vco_freq_per_sar_ref_clk
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};
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-static u32 async_mode_at_tf;
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-
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static u32 dq_bit_map_2_phy_pin[] = {
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1, 0, 2, 6, 9, 8, 3, 7, /* 0 */
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8, 9, 1, 7, 2, 6, 3, 0, /* 1 */
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@@ -734,7 +732,8 @@ static int ddr3_tip_a38x_set_divider(u8
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u32 divider = 0;
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u32 sar_val, ref_clk_satr;
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u32 async_val;
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- u32 freq = mv_ddr_freq_get(frequency);
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+ u32 cpu_freq;
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+ u32 ddr_freq = mv_ddr_freq_get(frequency);
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if (if_id != 0) {
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DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
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@@ -751,11 +750,14 @@ static int ddr3_tip_a38x_set_divider(u8
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ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG);
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if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) ==
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DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_25MHZ)
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- divider = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val] / freq;
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+ cpu_freq = a38x_vco_freq_per_sar_ref_clk_25_mhz[sar_val];
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else
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- divider = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val] / freq;
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+ cpu_freq = a38x_vco_freq_per_sar_ref_clk_40_mhz[sar_val];
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+
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+ divider = cpu_freq / ddr_freq;
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- if ((async_mode_at_tf == 1) && (freq > 400)) {
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+ if (((cpu_freq % ddr_freq != 0) || (divider != 2 && divider != 3)) &&
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+ (ddr_freq > 400)) {
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/* Set async mode */
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dunit_write(0x20220, 0x1000, 0x1000);
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dunit_write(0xe42f4, 0x200, 0x200);
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@@ -869,8 +871,6 @@ int ddr3_tip_ext_write(u32 dev_num, u32
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int mv_ddr_early_init(void)
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{
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- struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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-
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/* FIXME: change this configuration per ddr type
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* configure a380 and a390 to work with receiver odt timing
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* the odt_config is defined:
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@@ -882,9 +882,6 @@ int mv_ddr_early_init(void)
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mv_ddr_sw_db_init(0, 0);
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- if (tm->interface_params[0].memory_freq != MV_DDR_FREQ_SAR)
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- async_mode_at_tf = 1;
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-
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return MV_OK;
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}
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@ -1,92 +0,0 @@
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From d17ab6e1289b1d705c75de8a2351218962fb7352 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Thu, 9 Dec 2021 11:06:39 +0100
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Subject: [PATCH] nvme: Do not allocate 8kB buffer on stack
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Calling 'nvme scan' followed by 'nvme detail' crashes U-Boot on Turris
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Omnia with the following error:
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undefined instruction
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pc : [<0a000000>] lr : [<7ff80bfc>]
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reloc pc : [<8a8c0000>] lr : [<00840bfc>]
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sp : 7fb2b908 ip : 0000002a fp : 02000000
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r10: 04000000 r9 : 7fb2fed0 r8 : e1000000
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r7 : 0c000000 r6 : 03000000 r5 : 06000000 r4 : 01000000
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r3 : 7fb30928 r2 : 7fb30928 r1 : 00000000 r0 : 00000000
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Flags: nZCv IRQs off FIQs off Mode SVC_32
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Code: 0f0fb4f0 0f0fb4f0 0f0fb4f0 0f0fb4f0 (f0f04b0f)
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Resetting CPU ...
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|
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This happens when nvme_print_info() tries to return to the caller. It
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looks like this error is caused by trying to allocate 8 KiB of memory
|
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on the stack by the two uses of ALLOC_CACHE_ALIGN_BUFFER().
|
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|
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Use malloc_cache_aligned() to allocate this memory dynamically instead.
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|
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This fixes 'nvme detail' on Turris Omnia.
|
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|
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Note that similar change was applied to file drivers/nvme/nvme.c in past by
|
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commit 2f83481dff9c ("nvme: use page-aligned buffer for identify command").
|
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|
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Signed-off-by: Pali Rohár <pali@kernel.org>
|
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Signed-off-by: Marek Behún <marek.behun@nic.cz>
|
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---
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drivers/nvme/nvme_show.c | 35 ++++++++++++++++++++++++++---------
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1 file changed, 26 insertions(+), 9 deletions(-)
|
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|
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--- a/drivers/nvme/nvme_show.c
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+++ b/drivers/nvme/nvme_show.c
|
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@@ -106,24 +106,41 @@ int nvme_print_info(struct udevice *udev
|
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{
|
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struct nvme_ns *ns = dev_get_priv(udev);
|
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struct nvme_dev *dev = ns->dev;
|
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- ALLOC_CACHE_ALIGN_BUFFER(char, buf_ns, sizeof(struct nvme_id_ns));
|
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- struct nvme_id_ns *id = (struct nvme_id_ns *)buf_ns;
|
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- ALLOC_CACHE_ALIGN_BUFFER(char, buf_ctrl, sizeof(struct nvme_id_ctrl));
|
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- struct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf_ctrl;
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+ struct nvme_id_ctrl *ctrl;
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+ struct nvme_id_ns *id;
|
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+ int ret = 0;
|
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- if (nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl))
|
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- return -EIO;
|
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+ ctrl = memalign(dev->page_size, sizeof(struct nvme_id_ctrl));
|
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+ if (!ctrl)
|
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+ return -ENOMEM;
|
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+
|
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+ if (nvme_identify(dev, 0, 1, (dma_addr_t)(long)ctrl)) {
|
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+ ret = -EIO;
|
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+ goto free_ctrl;
|
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+ }
|
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|
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print_optional_admin_cmd(le16_to_cpu(ctrl->oacs), ns->devnum);
|
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print_optional_nvm_cmd(le16_to_cpu(ctrl->oncs), ns->devnum);
|
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print_format_nvme_attributes(ctrl->fna, ns->devnum);
|
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|
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- if (nvme_identify(dev, ns->ns_id, 0, (dma_addr_t)(long)id))
|
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- return -EIO;
|
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+ id = memalign(dev->page_size, sizeof(struct nvme_id_ns));
|
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+ if (!id) {
|
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+ ret = -ENOMEM;
|
||||
+ goto free_ctrl;
|
||||
+ }
|
||||
+
|
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+ if (nvme_identify(dev, ns->ns_id, 0, (dma_addr_t)(long)id)) {
|
||||
+ ret = -EIO;
|
||||
+ goto free_id;
|
||||
+ }
|
||||
|
||||
print_formats(id, ns);
|
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print_data_protect_cap(id->dpc, ns->devnum);
|
||||
print_metadata_cap(id->mc, ns->devnum);
|
||||
|
||||
- return 0;
|
||||
+free_id:
|
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+ free(id);
|
||||
+free_ctrl:
|
||||
+ free(ctrl);
|
||||
+ return ret;
|
||||
}
|
||||
@ -1,64 +0,0 @@
|
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From 0f3466f52fbacce67e147b9234e6323edff26a6d Mon Sep 17 00:00:00 2001
|
||||
From: Robert Marko <robert.marko@sartura.hr>
|
||||
Date: Fri, 11 Mar 2022 19:14:07 +0100
|
||||
Subject: [PATCH] mmc: xenon_sdhci: remove wait_dat0 SDHCI OP
|
||||
MIME-Version: 1.0
|
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
|
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|
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Generic SDHCI driver received support for checking the busy status by
|
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polling the DAT[0] level instead of waiting for the worst MMC switch time.
|
||||
|
||||
Unfortunately, it appears that this does not work for Xenon controllers
|
||||
despite being a part of the standard SDHCI registers and the Armada 3720
|
||||
datasheet itself telling that BIT(20) is useful for detecting the DAT[0]
|
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busy signal.
|
||||
|
||||
I have tried increasing the timeout value, but I have newer managed to
|
||||
catch DAT_LEVEL bits change from 0 at all.
|
||||
|
||||
This issue appears to hit most if not all SoC-s supported by Xenon driver,
|
||||
at least A3720, A8040 and CN9130 have non working eMMC currently.
|
||||
|
||||
So, until a better solution is found drop the wait_dat0 OP for Xenon.
|
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I was able to only test it on A3720, but it should work for others as well.
|
||||
|
||||
Fixes: 40e6f52454fc ("drivers: mmc: Add wait_dat0 support for sdhci driver")
|
||||
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
|
||||
Reviewed-by: Marek Behún <marek.behun@nic.cz>
|
||||
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
|
||||
Reviewed-by: Stefan Roese <sr@denx.de>
|
||||
---
|
||||
drivers/mmc/xenon_sdhci.c | 7 ++++++-
|
||||
1 file changed, 6 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/mmc/xenon_sdhci.c
|
||||
+++ b/drivers/mmc/xenon_sdhci.c
|
||||
@@ -439,6 +439,8 @@ static const struct sdhci_ops xenon_sdhc
|
||||
.set_ios_post = xenon_sdhci_set_ios_post
|
||||
};
|
||||
|
||||
+static struct dm_mmc_ops xenon_mmc_ops;
|
||||
+
|
||||
static int xenon_sdhci_probe(struct udevice *dev)
|
||||
{
|
||||
struct xenon_sdhci_plat *plat = dev_get_plat(dev);
|
||||
@@ -452,6 +454,9 @@ static int xenon_sdhci_probe(struct udev
|
||||
host->mmc->dev = dev;
|
||||
upriv->mmc = host->mmc;
|
||||
|
||||
+ xenon_mmc_ops = sdhci_ops;
|
||||
+ xenon_mmc_ops.wait_dat0 = NULL;
|
||||
+
|
||||
/* Set quirks */
|
||||
host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR;
|
||||
|
||||
@@ -568,7 +573,7 @@ U_BOOT_DRIVER(xenon_sdhci_drv) = {
|
||||
.id = UCLASS_MMC,
|
||||
.of_match = xenon_sdhci_ids,
|
||||
.of_to_plat = xenon_sdhci_of_to_plat,
|
||||
- .ops = &sdhci_ops,
|
||||
+ .ops = &xenon_mmc_ops,
|
||||
.bind = xenon_sdhci_bind,
|
||||
.probe = xenon_sdhci_probe,
|
||||
.remove = xenon_sdhci_remove,
|
||||
@ -1,65 +0,0 @@
|
||||
From c11428c7def52671f57089701efe878f7071b696 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
|
||||
Date: Thu, 17 Feb 2022 01:08:37 +0100
|
||||
Subject: [PATCH 1/3] ddr: marvell: a38x: fix BYTE_HOMOGENEOUS_SPLIT_OUT
|
||||
decision
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
In commit 3fc92a215b69 ("ddr: marvell: a38x: fix SPLIT_OUT_MIX state
|
||||
decision") I ported a cleaned up and changed version of patch
|
||||
mv_ddr: a380: fix SPLIT_OUT_MIX state decision
|
||||
|
||||
In the port we removed checking for BYTE_HOMOGENEOUS_SPLIT_OUT bit,
|
||||
because:
|
||||
- the fix seemed to work without it
|
||||
- the bit was checked for only at one place out of two, while the second
|
||||
bit, BYTE_SPLIT_OUT_MIX, was checked for in both cases
|
||||
- without the removal it didn't work on Allied Telesis' x530 board
|
||||
|
||||
We recently had a chance to test on more boards, and it seems that the
|
||||
change needs to be opposite: instead of removing the check for
|
||||
BYTE_HOMOGENEOUS_SPLIT_OUT from the first if() statement, the check
|
||||
needs to be added also to the second one - it needs to be at both
|
||||
places.
|
||||
|
||||
With this change all the Turris Omnia boards I have had available to
|
||||
test seem to work, I didn't encounter not even one failed DDR training.
|
||||
|
||||
As last time, I am noting that I do not understand what this code is
|
||||
actually doing, I haven't studied the DDR training algorithm and
|
||||
I suspect that no one will be able to explain it to U-Boot contributors,
|
||||
so we are left with this blind poking in the code with testing whether
|
||||
it works on several boards and hoping it doesn't break anything for
|
||||
anyone :-(.
|
||||
|
||||
Signed-off-by: Marek Behún <marek.behun@nic.cz>
|
||||
Tested-by: Chris Packham <judge.packham@gmail.com>
|
||||
Reviewed-by: Stefan Roese <sr@denx.de>
|
||||
---
|
||||
drivers/ddr/marvell/a38x/ddr3_training_centralization.c | 6 ++++--
|
||||
1 file changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
|
||||
+++ b/drivers/ddr/marvell/a38x/ddr3_training_centralization.c
|
||||
@@ -180,7 +180,8 @@ static int ddr3_tip_centralization(u32 d
|
||||
[bit_id],
|
||||
EDGE_1);
|
||||
if (current_byte_status &
|
||||
- BYTE_SPLIT_OUT_MIX) {
|
||||
+ (BYTE_SPLIT_OUT_MIX |
|
||||
+ BYTE_HOMOGENEOUS_SPLIT_OUT)) {
|
||||
if (cur_start_win[bit_id] >= 64)
|
||||
cur_start_win[bit_id] -= 64;
|
||||
else
|
||||
@@ -197,7 +198,8 @@ static int ddr3_tip_centralization(u32 d
|
||||
EDGE_1);
|
||||
if (cur_end_win[bit_id] >= 64 &&
|
||||
(current_byte_status &
|
||||
- BYTE_SPLIT_OUT_MIX)) {
|
||||
+ (BYTE_SPLIT_OUT_MIX |
|
||||
+ BYTE_HOMOGENEOUS_SPLIT_OUT))) {
|
||||
cur_end_win[bit_id] -= 64;
|
||||
DEBUG_CENTRALIZATION_ENGINE
|
||||
(DEBUG_LEVEL_INFO,
|
||||
@ -1,49 +0,0 @@
|
||||
From 74767a3875c99b1a3d2818456a5fdc02ec1e4f93 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
|
||||
Date: Thu, 17 Feb 2022 13:54:42 +0100
|
||||
Subject: [PATCH 2/3] arm: mvebu: spl: Add option to reset the board on DDR
|
||||
training failure
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Some boards may occacionally fail DDR training. Currently we hang() in
|
||||
this case. Add an option that makes the board do an immediate reset in
|
||||
such a case, so that a new training is tried as soon as possible,
|
||||
instead of hanging and possibly waiting for watchdog to reset the board.
|
||||
|
||||
(If the DDR training fails while booting the image via UART, we will
|
||||
still hang - it doesn't make sense to reset in such a case, because
|
||||
after reset the board will try booting from another medium, and the
|
||||
UART booting utility does not expect that.)
|
||||
|
||||
Signed-off-by: Marek Behún <marek.behun@nic.cz>
|
||||
Reviewed-by: Pali Rohár <pali@kernel.org>
|
||||
Reviewed-by: Stefan Roese <sr@denx.de>
|
||||
---
|
||||
arch/arm/mach-mvebu/spl.c | 7 ++++++-
|
||||
1 file changed, 6 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm/mach-mvebu/spl.c
|
||||
+++ b/arch/arm/mach-mvebu/spl.c
|
||||
@@ -4,6 +4,7 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
+#include <cpu_func.h>
|
||||
#include <dm.h>
|
||||
#include <debug_uart.h>
|
||||
#include <fdtdec.h>
|
||||
@@ -290,7 +291,11 @@ void board_init_f(ulong dummy)
|
||||
ret = ddr3_init();
|
||||
if (ret) {
|
||||
debug("ddr3_init() failed: %d\n", ret);
|
||||
- hang();
|
||||
+ if (IS_ENABLED(CONFIG_DDR_RESET_ON_TRAINING_FAILURE) &&
|
||||
+ get_boot_device() != BOOT_DEVICE_UART)
|
||||
+ reset_cpu();
|
||||
+ else
|
||||
+ hang();
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,38 +0,0 @@
|
||||
From 930c46e86123aeea1c73ae55d70ff3dcfc077992 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
|
||||
Date: Thu, 17 Feb 2022 13:54:43 +0100
|
||||
Subject: [PATCH 3/3] arm: mvebu: turris_omnia: Reset the board immediately on
|
||||
DDR training failure
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
The state of the current DDR training code for Armada 38x is such that
|
||||
we cannot be sure it will always train successfully - although after the
|
||||
last change we were yet unable to find a board that failed DDR training,
|
||||
from experience in the last 2 years we know that it is possible.
|
||||
|
||||
The experience also tells us that in many cases the board fails training
|
||||
only sometimes, and after a reset the training is successful.
|
||||
|
||||
Enable the new option that makes the board reset itself on DDR training
|
||||
failure immediately. Until now we called hang() in such a case, which
|
||||
meant that the board was reset by the MCU after 120 seconds.
|
||||
|
||||
Signed-off-by: Marek Behún <marek.behun@nic.cz>
|
||||
Reviewed-by: Stefan Roese <sr@denx.de>
|
||||
Reviewed-by: Pali Rohár <pali@kernel.org>
|
||||
---
|
||||
configs/turris_omnia_defconfig | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/configs/turris_omnia_defconfig
|
||||
+++ b/configs/turris_omnia_defconfig
|
||||
@@ -11,6 +11,7 @@ CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_SYS_MEMTEST_START=0x00800000
|
||||
CONFIG_SYS_MEMTEST_END=0x00ffffff
|
||||
CONFIG_TARGET_TURRIS_OMNIA=y
|
||||
+CONFIG_DDR_RESET_ON_TRAINING_FAILURE=y
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0xF0000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
Loading…
Reference in New Issue
Block a user