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ipq806x: RT4230W: utilize nvmem-cells for ath10k caldata

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Converts extraction entries from 11-ath10k-caldata into
nvmem-cells in the individual board's device-tree file.

Same as commit 2047058 ("ipq806x: utilize nvmem-cells
for pre-calibration data")

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Ansuel Smith <ansuelsmth@gmail.com>
This commit is contained in:
Chukun Pan 2022-02-10 21:26:40 +08:00 committed by Hauke Mehrtens
parent eee41e33ec
commit 45b3111b99
2 changed files with 66 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
View File

@ -17,9 +17,6 @@ case "$FIRMWARE" in
;; ;;
"ath10k/pre-cal-pci-0000:01:00.0.bin") "ath10k/pre-cal-pci-0000:01:00.0.bin")
case $board in case $board in
askey,rt4230w-rev6)
caldata_extract "0:ART" 0x1000 0x2f20
;;
asrock,g10) asrock,g10)
caldata_extract "0:art" 0x1000 0x2f20 caldata_extract "0:art" 0x1000 0x2f20
;; ;;
@ -40,9 +37,6 @@ case "$FIRMWARE" in
;; ;;
"ath10k/pre-cal-pci-0001:01:00.0.bin") "ath10k/pre-cal-pci-0001:01:00.0.bin")
case $board in case $board in
askey,rt4230w-rev6)
caldata_extract "0:ART" 0x5000 0x2f20
;;
asrock,g10) asrock,g10)
caldata_extract "0:art" 0x5000 0x2f20 caldata_extract "0:art" 0x5000 0x2f20
;; ;;

77
target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts
View File

@ -151,100 +151,139 @@
reg = <0x0000000 0x0040000>; reg = <0x0000000 0x0040000>;
read-only; read-only;
}; };
partition@40000 { partition@40000 {
label = "0:MIBIB"; label = "0:MIBIB";
reg = <0x0040000 0x0140000>; reg = <0x0040000 0x0140000>;
read-only; read-only;
}; };
partition@180000 { partition@180000 {
label = "0:SBL2"; label = "0:SBL2";
reg = <0x0180000 0x0140000>; reg = <0x0180000 0x0140000>;
read-only; read-only;
}; };
partition@2c0000 { partition@2c0000 {
label = "0:SBL3"; label = "0:SBL3";
reg = <0x02c0000 0x0280000>; reg = <0x02c0000 0x0280000>;
read-only; read-only;
}; };
partition@540000 { partition@540000 {
label = "0:DDRCONFIG"; label = "0:DDRCONFIG";
reg = <0x0540000 0x0120000>; reg = <0x0540000 0x0120000>;
read-only; read-only;
}; };
partition@660000 { partition@660000 {
label = "0:SSD"; label = "0:SSD";
reg = <0x0660000 0x0120000>; reg = <0x0660000 0x0120000>;
read-only; read-only;
}; };
partition@780000 { partition@780000 {
label = "0:TZ"; label = "0:TZ";
reg = <0x0780000 0x0280000>; reg = <0x0780000 0x0280000>;
read-only; read-only;
}; };
partition@a00000 { partition@a00000 {
label = "0:RPM"; label = "0:RPM";
reg = <0x0a00000 0x0280000>; reg = <0x0a00000 0x0280000>;
read-only; read-only;
}; };
partition@c80000 { partition@c80000 {
label = "0:APPSBL"; label = "0:APPSBL";
reg = <0x0c80000 0x0500000>; reg = <0x0c80000 0x0500000>;
read-only; read-only;
}; };
partition@1180000 { partition@1180000 {
label = "0:APPSBLENV"; label = "0:APPSBLENV";
reg = <0x1180000 0x0080000>; reg = <0x1180000 0x0080000>;
}; };
ART: partition@1200000 {
partition@1200000 {
label = "0:ART"; label = "0:ART";
reg = <0x1200000 0x0140000>; reg = <0x1200000 0x0140000>;
read-only; read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_ART_0: macaddr@0 {
reg = <0x0 0x6>;
}; };
macaddr_ART_6: macaddr@6 {
reg = <0x6 0x6>;
};
precal_ART_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_ART_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
partition@1340000 { partition@1340000 {
label = "0:BOOTCONFIG"; label = "0:BOOTCONFIG";
reg = <0x1340000 0x0060000>; reg = <0x1340000 0x0060000>;
read-only; read-only;
}; };
partition@13a0000 { partition@13a0000 {
label = "0:SBL2_1"; label = "0:SBL2_1";
reg = <0x13a0000 0x0140000>; reg = <0x13a0000 0x0140000>;
read-only; read-only;
}; };
partition@14e0000 { partition@14e0000 {
label = "0:SBL3_1"; label = "0:SBL3_1";
reg = <0x14e0000 0x0280000>; reg = <0x14e0000 0x0280000>;
read-only; read-only;
}; };
partition@1760000 { partition@1760000 {
label = "0:DDRCONFIG_1"; label = "0:DDRCONFIG_1";
reg = <0x1760000 0x0120000>; reg = <0x1760000 0x0120000>;
read-only; read-only;
}; };
partition@1880000 { partition@1880000 {
label = "0:SSD_1"; label = "0:SSD_1";
reg = <0x1880000 0x0120000>; reg = <0x1880000 0x0120000>;
read-only; read-only;
}; };
partition@19a0000 { partition@19a0000 {
label = "0:TZ_1"; label = "0:TZ_1";
reg = <0x19a0000 0x0280000>; reg = <0x19a0000 0x0280000>;
read-only; read-only;
}; };
partition@1c20000 { partition@1c20000 {
label = "0:RPM_1"; label = "0:RPM_1";
reg = <0x1c20000 0x0280000>; reg = <0x1c20000 0x0280000>;
read-only; read-only;
}; };
partition@1ea0000 { partition@1ea0000 {
label = "0:BOOTCONFIG1"; label = "0:BOOTCONFIG1";
reg = <0x1ea0000 0x0060000>; reg = <0x1ea0000 0x0060000>;
read-only; read-only;
}; };
partition@1f00000 { partition@1f00000 {
label = "0:APPSBL_1"; label = "0:APPSBL_1";
reg = <0x1f00000 0x0500000>; reg = <0x1f00000 0x0500000>;
read-only; read-only;
}; };
partition@2400000 { partition@2400000 {
label = "ubi"; label = "ubi";
reg = <0x2400000 0x1a000000>; reg = <0x2400000 0x1a000000>;
@ -323,6 +362,21 @@
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_pins>; pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi0: wifi@1,0 {
compatible = "pci168c,0046";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&precal_ART_1000>;
nvmem-cell-names = "pre-calibration";
};
};
}; };
&pcie1 { &pcie1 {
@ -331,18 +385,19 @@
pinctrl-0 = <&pcie1_pins>; pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
max-link-speed = <1>; max-link-speed = <1>;
};
&ART { bridge@0,0 {
compatible = "nvmem-cells"; reg = <0x00000000 0 0 0 0>;
#address-cells = <1>; #address-cells = <3>;
#size-cells = <1>; #size-cells = <2>;
ranges;
macaddr_ART_0: macaddr@0 { wifi1: wifi@1,0 {
reg = <0x0 0x6>; compatible = "pci168c,0046";
}; reg = <0x00010000 0 0 0 0>;
macaddr_ART_6: macaddr@6 { nvmem-cells = <&precal_ART_5000>;
reg = <0x6 0x6>; nvmem-cell-names = "pre-calibration";
};
}; };
}; };