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tegra: correct cpu subtype 

Tegra 2 processors have only 16 double-precision registers. The change
introduced by 8dcc108760 ("toolchain: ARM: Fix toolchain compilation
for gcc 8.x") switched accidentally the toolchain for tegra target to cpu
type with 32 double-precision registers. This stems from gcc defaults
which assume "vfpv3-d32" if only "vfpv3" as mfpu is specified. That
change resulted in unusable image, in which kernel will kill userspace as
soon as it causing "Illegal instruction".

Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272
Fixes: 8dcc108760 ("toolchain: ARM: Fix toolchain compilation for
gcc 8.x")
Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
This commit is contained in:
Tomasz Maciej Nowak 2020-03-18 19:04:13 +01:00 committed by Petr Štetiar
parent 258f070d1a
commit 43d1d88510
1 changed files with 1 additions and 1 deletions
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2
target/linux/tegra/Makefile
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@ -11,7 +11,7 @@ BOARD := tegra
BOARDNAME := NVIDIA Tegra BOARDNAME := NVIDIA Tegra
FEATURES := audio boot-part display ext4 fpu gpio pci pcie rootfs-part rtc squashfs usb FEATURES := audio boot-part display ext4 fpu gpio pci pcie rootfs-part rtc squashfs usb
CPU_TYPE := cortex-a9 CPU_TYPE := cortex-a9
CPU_SUBTYPE := vfpv3 CPU_SUBTYPE := vfpv3-d16
KERNEL_PATCHVER := 5.4 KERNEL_PATCHVER := 5.4
KERNEL_TESTING_PATCHVER := 5.4 KERNEL_TESTING_PATCHVER := 5.4