airoha: en7581: refresh and fix PWM patch
Refresh and fix PWM patch with new revision proposed upstream. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit is contained in:
Christian Marangi
parent
b6bbc76c0b
commit
43d07feb91
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@ -1,18 +1,19 @@
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From b235c45e83c8c2a24746652982d569896b142de9 Mon Sep 17 00:00:00 2001
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From 97e4e7b106b08373f90ff1b8c4daf6c2254386a8 Mon Sep 17 00:00:00 2001
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From: Benjamin Larsson <benjamin.larsson@genexis.eu>
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Date: Wed, 16 Oct 2024 12:07:34 +0200
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Subject: [PATCH 2/2] pwm: airoha: Add support for EN7581 SoC
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Date: Wed, 23 Oct 2024 01:20:06 +0200
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Subject: [PATCH] pwm: airoha: Add support for EN7581 SoC
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Introduce driver for PWM module available on EN7581 SoC.
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Signed-off-by: Benjamin Larsson <benjamin.larsson@genexis.eu>
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Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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---
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drivers/pwm/Kconfig | 11 +
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drivers/pwm/Kconfig | 11 ++
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drivers/pwm/Makefile | 1 +
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drivers/pwm/pwm-airoha.c | 424 +++++++++++++++++++++++++++++++++++++++
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3 files changed, 436 insertions(+)
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drivers/pwm/pwm-airoha.c | 386 +++++++++++++++++++++++++++++++++++++++
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3 files changed, 398 insertions(+)
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create mode 100644 drivers/pwm/pwm-airoha.c
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--- a/drivers/pwm/Kconfig
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@ -47,7 +48,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
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--- /dev/null
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+++ b/drivers/pwm/pwm-airoha.c
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@@ -0,0 +1,424 @@
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@@ -0,0 +1,400 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright 2022 Markus Gothe <markus.gothe@genexis.eu>
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@ -80,11 +81,12 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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+#define SGPIO_LED_DATA_DATA GENMASK(16, 0)
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+
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+#define REG_SGPIO_CLK_DIVR 0x0028
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+#define REG_SGPIO_CLK_DIVR_MASK GENMASK(1, 0)
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+#define REG_SGPIO_CLK_DLY 0x002c
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+
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+#define REG_SIPO_FLASH_MODE_CFG 0x0030
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+#define SERIAL_GPIO_FLASH_MODE BIT(1)
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+#define SERIAL_GPIO_MODE BIT(0)
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+#define SERIAL_GPIO_MODE_74HC164 BIT(0)
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+
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+#define REG_GPIO_FLASH_PRD_SET(_n) (0x003c + ((_n) << 2))
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+#define GPIO_FLASH_PRD_MASK(_n) GENMASK(15 + ((_n) << 4), ((_n) << 4))
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@ -98,7 +100,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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+#define REG_CYCLE_CFG_VALUE(_n) (0x0098 + ((_n) << 2))
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+#define WAVE_GEN_CYCLE_MASK(_n) GENMASK(7 + ((_n) << 3), ((_n) << 3))
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+
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+#define EN7581_NUM_BUCKETS 8
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+#define PWM_NUM_BUCKETS 8
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+
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+struct airoha_pwm_bucket {
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+ /* Bitmask of PWM channels using this bucket */
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@ -115,7 +117,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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+ struct device_node *np;
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+ u64 initialized;
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+
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+ struct airoha_pwm_bucket bucket[EN7581_NUM_BUCKETS];
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+ struct airoha_pwm_bucket bucket[PWM_NUM_BUCKETS];
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+};
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+
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+/*
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@ -200,62 +202,25 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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+
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+static int airoha_pwm_sipo_init(struct airoha_pwm *pc)
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+{
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+ u32 clk_divr_val, sipo_clock_delay, sipo_clock_divisor;
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+ u32 val;
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+
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+ if (!(pc->initialized >> PWM_NUM_GPIO))
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+ return 0;
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+
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+ /*
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+ * Select the right shift register chip.
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+ * By default 74HC164 is assumed. With this enabled
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+ * 74HC595 chip is used that requires the latch pin
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+ * to be triggered to apply the configuration.
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+ */
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+ if (of_property_read_bool(pc->np, "airoha,74hc595-mode"))
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+ regmap_set_bits(pc->regmap, REG_SIPO_FLASH_MODE_CFG,
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+ SERIAL_GPIO_MODE);
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+ else
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+ regmap_clear_bits(pc->regmap, REG_SIPO_FLASH_MODE_CFG,
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+ SERIAL_GPIO_MODE);
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+ regmap_clear_bits(pc->regmap, REG_SIPO_FLASH_MODE_CFG,
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+ SERIAL_GPIO_MODE_74HC164);
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+
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+ if (of_property_read_u32(pc->np, "airoha,sipo-clock-divisor",
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+ &sipo_clock_divisor))
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+ sipo_clock_divisor = 32;
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+
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+ switch (sipo_clock_divisor) {
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+ case 4:
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+ clk_divr_val = 0;
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+ break;
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+ case 8:
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+ clk_divr_val = 1;
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+ break;
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+ case 16:
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+ clk_divr_val = 2;
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+ break;
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+ case 32:
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+ clk_divr_val = 3;
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+ break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ /* Configure shift register timings */
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+ regmap_write(pc->regmap, REG_SGPIO_CLK_DIVR, clk_divr_val);
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+
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+ if (of_property_read_u32(pc->np, "airoha,sipo-clock-delay",
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+ &sipo_clock_delay))
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+ sipo_clock_delay = 1;
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+
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+ if (sipo_clock_delay < 1 || sipo_clock_delay > sipo_clock_divisor / 2)
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+ return -EINVAL;
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+ /* Configure shift register timings, use 32x divisor */
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+ regmap_write(pc->regmap, REG_SGPIO_CLK_DIVR,
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+ FIELD_PREP(REG_SGPIO_CLK_DIVR_MASK, 0x3));
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+
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+ /*
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+ * The actual delay is sclkdly + 1 so subtract 1 from
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+ * sipo-clock-delay to calculate the register value
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+ * The actual delay is clock + 1.
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+ * Notice that clock delay should not be greater
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+ * than (divisor / 2) - 1.
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+ * Set to 0 by default. (aka 1)
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+ */
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+ sipo_clock_delay--;
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+ regmap_write(pc->regmap, REG_SGPIO_CLK_DLY, sipo_clock_delay);
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+ regmap_write(pc->regmap, REG_SGPIO_CLK_DLY, 0x0);
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+
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+ /*
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+ * It it necessary to after muxing explicitly shift out all
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@ -365,7 +330,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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+
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+static void airoha_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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+{
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+ struct airoha_pwm *pc = pwmchip_get_drvdata(chip);
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+ struct airoha_pwm *pc = container_of(chip, struct airoha_pwm, chip);
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+
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+ /* Disable PWM and release the waveform */
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+ airoha_pwm_config_flash_map(pc, pwm->hwpwm, -1);
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@ -380,7 +345,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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+static int airoha_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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+ const struct pwm_state *state)
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+{
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+ struct airoha_pwm *pc = pwmchip_get_drvdata(chip);
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+ struct airoha_pwm *pc = container_of(chip, struct airoha_pwm, chip);
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+ u64 duty = state->enabled ? state->duty_cycle : 0;
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+ u64 period = state->period;
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+
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@ -405,7 +370,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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+static int airoha_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
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+ struct pwm_state *state)
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+{
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+ struct airoha_pwm *pc = pwmchip_get_drvdata(chip);
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+ struct airoha_pwm *pc = container_of(chip, struct airoha_pwm, chip);
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+ int i;
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+
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+ /* find hwpwm in waveform generator bucket */
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@ -428,28 +393,39 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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+static const struct pwm_ops airoha_pwm_ops = {
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+ .get_state = airoha_pwm_get_state,
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+ .apply = airoha_pwm_apply,
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+ .owner = THIS_MODULE,
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+};
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+
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+static int airoha_pwm_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct airoha_pwm *pc;
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+ struct pwm_chip *chip;
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+
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+ chip = devm_pwmchip_alloc(dev, PWM_NUM_GPIO + PWM_NUM_SIPO,
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+ sizeof(*pc));
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+ if (IS_ERR(chip))
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+ return PTR_ERR(chip);
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+ pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
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+ if (!pc)
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+ return -ENOMEM;
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+
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+ chip->ops = &airoha_pwm_ops;
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+ pc = pwmchip_get_drvdata(chip);
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+ pc->np = dev->of_node;
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+ pc->chip.dev = dev;
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+ pc->chip.ops = &airoha_pwm_ops;
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+ pc->chip.npwm = PWM_NUM_GPIO + PWM_NUM_SIPO;
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+
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+ pc->regmap = device_node_to_regmap(dev->parent->of_node);
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+ if (IS_ERR(pc->regmap))
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+ return PTR_ERR(pc->regmap);
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+
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+ return devm_pwmchip_add(&pdev->dev, chip);
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+ platform_set_drvdata(pdev, pc);
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+
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+ return pwmchip_add(&pc->chip);
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+}
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+
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+static int airoha_pwm_remove(struct platform_device *pdev)
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+{
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+ struct airoha_pwm *pc = platform_get_drvdata(pdev);
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+
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+ pwmchip_remove(&pc->chip);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id airoha_pwm_of_match[] = {
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@ -464,6 +440,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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+ .of_match_table = airoha_pwm_of_match,
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+ },
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+ .probe = airoha_pwm_probe,
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+ .remove = airoha_pwm_remove,
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+};
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+module_platform_driver(airoha_pwm_driver);
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+
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