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realtek: update watchdog timer patch
The Realtek Otto watchdog timer driver was accepted upstream, and is queued for 5.17. Update the patch's file name, and replace by the final version. Signed-off-by: Sander Vanheule <sander@svanheule.net>
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@ -1,10 +1,7 @@
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From 2dbf0c6e0eebf523008c15794434d2d1a9b1260e Mon Sep 17 00:00:00 2001
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From 293903b9dfe43520f01374dc1661be11d6838c49 Mon Sep 17 00:00:00 2001
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Message-Id: <2dbf0c6e0eebf523008c15794434d2d1a9b1260e.1636018117.git.sander@svanheule.net>
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In-Reply-To: <cover.1636018117.git.sander@svanheule.net>
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References: <cover.1636018117.git.sander@svanheule.net>
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From: Sander Vanheule <sander@svanheule.net>
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From: Sander Vanheule <sander@svanheule.net>
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Date: Sun, 3 Oct 2021 09:25:27 +0200
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Date: Thu, 18 Nov 2021 17:29:52 +0100
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Subject: [PATCH v3 2/2] watchdog: Add Realtek Otto watchdog timer
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Subject: watchdog: Add Realtek Otto watchdog timer
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Realtek MIPS SoCs (platform name Otto) have a watchdog timer with
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Realtek MIPS SoCs (platform name Otto) have a watchdog timer with
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pretimeout notifitication support. The WDT can (partially) hard reset,
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pretimeout notifitication support. The WDT can (partially) hard reset,
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@ -22,12 +19,15 @@ supported platforms. This means that the phase2 interrupt will only fire
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at the same time as reset, so implementing phase2 is of little use.
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at the same time as reset, so implementing phase2 is of little use.
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Signed-off-by: Sander Vanheule <sander@svanheule.net>
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Signed-off-by: Sander Vanheule <sander@svanheule.net>
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Reviewed-by: Guenter Roeck <linux@roeck-us.net>
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Link: https://lore.kernel.org/r/6d060bccbdcc709cfa79203485db85aad3c3beb5.1637252610.git.sander@svanheule.net
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Signed-off-by: Guenter Roeck <linux@roeck-us.net>
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---
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---
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MAINTAINERS | 7 +
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MAINTAINERS | 7 +
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drivers/watchdog/Kconfig | 13 +
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drivers/watchdog/Kconfig | 13 ++
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drivers/watchdog/Makefile | 1 +
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drivers/watchdog/Makefile | 1 +
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drivers/watchdog/realtek_otto_wdt.c | 361 ++++++++++++++++++++++++++++
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drivers/watchdog/realtek_otto_wdt.c | 384 ++++++++++++++++++++++++++++++++++++
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4 files changed, 382 insertions(+)
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4 files changed, 405 insertions(+)
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create mode 100644 drivers/watchdog/realtek_otto_wdt.c
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create mode 100644 drivers/watchdog/realtek_otto_wdt.c
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--- a/MAINTAINERS
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--- a/MAINTAINERS
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@ -80,7 +80,7 @@ Signed-off-by: Sander Vanheule <sander@svanheule.net>
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--- /dev/null
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--- /dev/null
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+++ b/drivers/watchdog/realtek_otto_wdt.c
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+++ b/drivers/watchdog/realtek_otto_wdt.c
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@@ -0,0 +1,361 @@
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@@ -0,0 +1,384 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+// SPDX-License-Identifier: GPL-2.0-only
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+
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+
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+/*
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+/*
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@ -150,7 +150,7 @@ Signed-off-by: Sander Vanheule <sander@svanheule.net>
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+ struct watchdog_device wdev;
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+ struct watchdog_device wdev;
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+ struct device *dev;
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+ struct device *dev;
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+ void __iomem *base;
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+ void __iomem *base;
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+ struct clk *clk;
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+ unsigned int clk_rate_khz;
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+ int irq_phase1;
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+ int irq_phase1;
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+};
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+};
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+
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+
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@ -189,12 +189,7 @@ Signed-off-by: Sander Vanheule <sander@svanheule.net>
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+
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+
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+static int otto_wdt_tick_ms(struct otto_wdt_ctrl *ctrl, int prescale)
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+static int otto_wdt_tick_ms(struct otto_wdt_ctrl *ctrl, int prescale)
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+{
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+{
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+ unsigned int rate_khz = clk_get_rate(ctrl->clk) / 1000;
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+ return DIV_ROUND_CLOSEST(1 << (25 + prescale), ctrl->clk_rate_khz);
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+
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+ if (!rate_khz)
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+ return 0;
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+
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+ return DIV_ROUND_CLOSEST(1 << (25 + prescale), rate_khz);
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+}
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+}
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+
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+
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+/*
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+/*
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@ -323,6 +318,34 @@ Signed-off-by: Sander Vanheule <sander@svanheule.net>
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+ WDIOF_PRETIMEOUT,
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+ WDIOF_PRETIMEOUT,
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+};
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+};
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+
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+
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+static void otto_wdt_clock_action(void *data)
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+{
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+ clk_disable_unprepare(data);
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+}
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+
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+static int otto_wdt_probe_clk(struct otto_wdt_ctrl *ctrl)
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+{
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+ struct clk *clk = devm_clk_get(ctrl->dev, NULL);
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+ int ret;
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+
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+ if (IS_ERR(clk))
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+ return dev_err_probe(ctrl->dev, PTR_ERR(clk), "Failed to get clock\n");
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+
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+ ret = clk_prepare_enable(clk);
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+ if (ret)
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+ return dev_err_probe(ctrl->dev, ret, "Failed to enable clock\n");
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+
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+ ret = devm_add_action_or_reset(ctrl->dev, otto_wdt_clock_action, clk);
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+ if (ret)
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+ return ret;
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+
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+ ctrl->clk_rate_khz = clk_get_rate(clk) / 1000;
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+ if (ctrl->clk_rate_khz == 0)
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+ return dev_err_probe(ctrl->dev, -ENXIO, "Failed to get clock rate\n");
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+
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+ return 0;
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+}
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+
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+static int otto_wdt_probe_reset_mode(struct otto_wdt_ctrl *ctrl)
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+static int otto_wdt_probe_reset_mode(struct otto_wdt_ctrl *ctrl)
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+{
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+{
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+ static const char *mode_property = "realtek,reset-mode";
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+ static const char *mode_property = "realtek,reset-mode";
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@ -380,13 +403,13 @@ Signed-off-by: Sander Vanheule <sander@svanheule.net>
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+ ctrl->base + OTTO_WDT_REG_INTR);
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+ ctrl->base + OTTO_WDT_REG_INTR);
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+ iowrite32(OTTO_WDT_CTRL_DEFAULT, ctrl->base + OTTO_WDT_REG_CTRL);
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+ iowrite32(OTTO_WDT_CTRL_DEFAULT, ctrl->base + OTTO_WDT_REG_CTRL);
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+
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+
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+ ctrl->clk = devm_clk_get(dev, NULL);
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+ ret = otto_wdt_probe_clk(ctrl);
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+ if (IS_ERR(ctrl->clk))
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+ if (ret)
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+ return dev_err_probe(dev, PTR_ERR(ctrl->clk), "Failed to get clock\n");
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+ return ret;
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+
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+
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+ ctrl->irq_phase1 = platform_get_irq_byname(pdev, "phase1");
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+ ctrl->irq_phase1 = platform_get_irq_byname(pdev, "phase1");
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+ if (ctrl->irq_phase1 < 0)
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+ if (ctrl->irq_phase1 < 0)
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+ return dev_err_probe(dev, ctrl->irq_phase1, "phase1 IRQ not found\n");
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+ return ctrl->irq_phase1;
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+
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+
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+ ret = devm_request_irq(dev, ctrl->irq_phase1, otto_wdt_phase1_isr, 0,
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+ ret = devm_request_irq(dev, ctrl->irq_phase1, otto_wdt_phase1_isr, 0,
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+ "realtek-otto-wdt", ctrl);
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+ "realtek-otto-wdt", ctrl);
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@ -403,7 +426,7 @@ Signed-off-by: Sander Vanheule <sander@svanheule.net>
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+
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+
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+ /*
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+ /*
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+ * Since pretimeout cannot be disabled, min. timeout is twice the
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+ * Since pretimeout cannot be disabled, min. timeout is twice the
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+ * subsystem resolution. max. timeout is ca. 43s at a bus clock of 200MHz.
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+ * subsystem resolution. Max. timeout is ca. 43s at a bus clock of 200MHz.
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+ */
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+ */
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+ ctrl->wdev.min_timeout = 2;
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+ ctrl->wdev.min_timeout = 2;
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+ max_tick_ms = otto_wdt_tick_ms(ctrl, OTTO_WDT_PRESCALE_MAX);
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+ max_tick_ms = otto_wdt_tick_ms(ctrl, OTTO_WDT_PRESCALE_MAX);
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