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apm821xx: fix bogus key-presses on boot

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"There are often transient line events when
the system is powered up and initialized and it
is often necessary for the gpio_chip driver to
clear any interrupt flags in hardware before
setting up the gpio chip, especially the
irqchip portions of it."
<http://lists.infradead.org/pipermail/openwrt-devel/2019-June/017630.html>

This patch adds a fix for the APM821XX's interrupt
controller to clear any bogus pending toggled
interrupts that happens on various APM821XX boards
on boot.

The patch also changes the debouce-interval from the
default 5ms debounce interval to 60ms all around.
The default setting caused on occasions that the button
state became stuck in a pressed state, even though the
button was released.

Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
(backported from commit 971f31bedc)
This commit is contained in:
Christian Lamparter 2019-06-15 19:13:30 +02:00 committed by Jo-Philipp Wich
parent f79e6e01bd
commit 40379b0ec6
1 changed files with 30 additions and 0 deletions
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30
target/linux/apm821xx/patches-4.14/100-powerpc-4xx-uic-clear-pending-interrupt-after-irq-ty.patch Normal file
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From 9b84ad676e248a3e3c81db7f5d39e1739b3780aa Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sat, 15 Jun 2019 16:35:26 +0200
Subject: [PATCH] powerpc/4xx/uic: clear pending interrupt after irq type/pol
change
When testing out gpio-keys with a button, a spurious
interrupt (and therefore a key press or release event)
gets triggered as soon as the driver enables the irq
line for the first time.
This patch clears any potential bogus generated interrupt
that was caused by the switching of the associated irq's
type and polarity.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/powerpc/platforms/4xx/uic.c | 1 +
1 file changed, 1 insertion(+)
--- a/arch/powerpc/platforms/4xx/uic.c
+++ b/arch/powerpc/platforms/4xx/uic.c
@@ -158,6 +158,7 @@ static int uic_set_irq_type(struct irq_d
mtdcr(uic->dcrbase + UIC_PR, pr);
mtdcr(uic->dcrbase + UIC_TR, tr);
+ mtdcr(uic->dcrbase + UIC_SR, ~mask);
raw_spin_unlock_irqrestore(&uic->lock, flags);