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rbcfg: Implement CPU frequency control
This patch implements CPU frequency control as found on several routerboard devices. Supported SoCs: - QCA953X - AR9344 Tested on hAP lite and mAP lite (QCA953x): steps of 50MHz Tested on LHG 5 (AR9344): steps of 50MHz On unsupported hardware, this patch is a NOP: it will not alter the new field. "rbcfg help" will display an empty "cpu_freq" help listing. "rbcfg show" will not show the cpu_freq field. "rbcfg set/get cpu_freq" will return an error code. Signed-off-by: Thibaut VARENE <hacks@slashdirt.org> [adjusted subject] Signed-off-by: Jo-Philipp Wich <jo@mein.io>
This commit is contained in:
Thibaut VARENE
Jo-Philipp Wich
parent
b9c31c44d7
commit
2be307c998
@ -8,7 +8,7 @@
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include $(TOPDIR)/rules.mk
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PKG_NAME:=rbcfg
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PKG_RELEASE:=1
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PKG_RELEASE:=2
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PKG_BUILD_DIR := $(BUILD_DIR)/$(PKG_NAME)
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@ -2,6 +2,7 @@
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* RouterBOOT configuration utility
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*
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* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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@ -29,6 +30,7 @@
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#define RB_ERR_INVALID 2
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#define RB_ERR_NOMEM 3
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#define RB_ERR_IO 4
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#define RB_ERR_NOTWANTED 5
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#define ARRAY_SIZE(_a) (sizeof((_a)) / sizeof((_a)[0]))
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@ -67,6 +69,11 @@ struct rbcfg_command {
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int (*exec)(int argc, const char *argv[]);
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};
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struct rbcfg_soc {
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const char *needle;
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const int type;
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};
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static void usage(void);
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/* Globals */
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@ -135,12 +142,32 @@ static const struct rbcfg_value rbcfg_cpu_mode[] = {
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RB_CPU_MODE_REGULAR),
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};
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static const struct rbcfg_value rbcfg_cpu_freq_dummy[] = {
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};
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static const struct rbcfg_value rbcfg_cpu_freq_qca953x[] = {
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CFG_U32("-2", "-100MHz", RB_CPU_FREQ_L2),
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CFG_U32("-1", "- 50MHz", RB_CPU_FREQ_L1),
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CFG_U32("0", "Factory", RB_CPU_FREQ_N0),
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CFG_U32("+1", "+ 50MHz", RB_CPU_FREQ_H1),
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CFG_U32("+2", "+100MHz", RB_CPU_FREQ_H2),
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};
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static const struct rbcfg_value rbcfg_cpu_freq_ar9344[] = {
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CFG_U32("-2", "-100MHz", RB_CPU_FREQ_L2),
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CFG_U32("-1", "- 50MHz", RB_CPU_FREQ_L1),
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CFG_U32("0", "Factory", RB_CPU_FREQ_N0),
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CFG_U32("+1", "+ 50MHz", RB_CPU_FREQ_H1),
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CFG_U32("+2", "+100MHz", RB_CPU_FREQ_H2),
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CFG_U32("+3", "+150MHz", RB_CPU_FREQ_H3),
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};
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static const struct rbcfg_value rbcfg_booter[] = {
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CFG_U32("regular", "load regular booter", RB_BOOTER_REGULAR),
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CFG_U32("backup", "force backup-booter loading", RB_BOOTER_BACKUP),
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};
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static const struct rbcfg_env rbcfg_envs[] = {
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static struct rbcfg_env rbcfg_envs[] = {
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{
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.name = "boot_delay",
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.id = RB_ID_BOOT_DELAY,
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@ -177,6 +204,12 @@ static const struct rbcfg_env rbcfg_envs[] = {
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.type = RBCFG_ENV_TYPE_U32,
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.values = rbcfg_cpu_mode,
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.num_values = ARRAY_SIZE(rbcfg_cpu_mode),
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}, {
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.name = "cpu_freq",
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.id = RB_ID_CPU_FREQ,
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.type = RBCFG_ENV_TYPE_U32,
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.values = rbcfg_cpu_freq_dummy,
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.num_values = ARRAY_SIZE(rbcfg_cpu_freq_dummy),
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}, {
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.name = "uart_speed",
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.id = RB_ID_UART_SPEED,
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@ -240,8 +273,10 @@ rbcfg_find_tag(struct rbcfg_ctx *ctx, uint16_t tag_id, uint16_t *tag_len,
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buf += 2;
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buflen -= 2;
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if (id == RB_ID_TERMINATOR)
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if (id == RB_ID_TERMINATOR) {
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ret = RB_ERR_NOTWANTED;
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break;
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}
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if (buflen < len)
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break;
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@ -257,7 +292,7 @@ rbcfg_find_tag(struct rbcfg_ctx *ctx, uint16_t tag_id, uint16_t *tag_len,
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buflen -= len;
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}
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if (ret)
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if (RB_ERR_NOTFOUND == ret)
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fprintf(stderr, "no tag found with id=%u\n", tag_id);
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return ret;
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@ -748,6 +783,96 @@ usage(void)
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fprintf(stderr, "\n");
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}
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#define RBCFG_SOC_UNKNOWN 0
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#define RBCFG_SOC_QCA953X 1
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#define RBCFG_SOC_AR9344 2
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static const struct rbcfg_soc rbcfg_socs[] = {
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{
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.needle = "QCA953",
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.type = RBCFG_SOC_QCA953X,
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}, {
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.needle = "AR9344",
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.type = RBCFG_SOC_AR9344,
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},
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};
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#define CPUINFO_BUFSIZE 128 /* lines of interest are < 80 chars */
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static int cpuinfo_find_soc(void)
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{
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FILE *fp;
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char temp[CPUINFO_BUFSIZE];
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char *haystack, *needle;
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int i, found = 0, soc_type = RBCFG_SOC_UNKNOWN;
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fp = fopen("/proc/cpuinfo", "r");
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if (!fp)
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goto end;
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/* first, extract the system type line */
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needle = "system type";
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while(fgets(temp, CPUINFO_BUFSIZE, fp)) {
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if (!strncmp(temp, needle, strlen(needle))) {
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found = 1;
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break;
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}
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}
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fclose(fp);
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/* failsafe in case cpuinfo format changes */
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if (!found)
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goto end;
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/* skip the field header */
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haystack = strchr(temp, ':');
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/* then, try to identify known SoC, stop at first match */
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for (i = 0; i < ARRAY_SIZE(rbcfg_socs); i++) {
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if ((strstr(haystack, rbcfg_socs[i].needle))) {
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soc_type = rbcfg_socs[i].type;
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break;
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}
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}
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end:
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return soc_type;
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}
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static void fixup_rbcfg_envs(void)
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{
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int i, num_val, soc_type;
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const struct rbcfg_value * env_value;
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/* detect SoC */
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soc_type = cpuinfo_find_soc();
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/* update rbcfg_envs */
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switch (soc_type) {
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case RBCFG_SOC_QCA953X:
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env_value = rbcfg_cpu_freq_qca953x;
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num_val = ARRAY_SIZE(rbcfg_cpu_freq_qca953x);
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break;
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case RBCFG_SOC_AR9344:
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env_value = rbcfg_cpu_freq_ar9344;
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num_val = ARRAY_SIZE(rbcfg_cpu_freq_ar9344);
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break;
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}
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for (i = 0; i < ARRAY_SIZE(rbcfg_envs); i++) {
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if (RB_ID_CPU_FREQ == rbcfg_envs[i].id) {
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if (RBCFG_SOC_UNKNOWN == soc_type)
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rbcfg_envs[i].id = RB_ID_TERMINATOR;
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else {
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rbcfg_envs[i].values = env_value;
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rbcfg_envs[i].num_values = num_val;
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}
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break;
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}
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}
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}
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int main(int argc, const char *argv[])
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{
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const struct rbcfg_command *cmd = NULL;
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@ -756,6 +881,8 @@ int main(int argc, const char *argv[])
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rbcfg_name = (char *) argv[0];
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fixup_rbcfg_envs();
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if (argc < 2) {
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usage();
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return EXIT_FAILURE;
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@ -32,6 +32,7 @@
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#define RB_ID_BOOT_PROTOCOL 9
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#define RB_ID_SOFT_10 10
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#define RB_ID_SOFT_11 11
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#define RB_ID_CPU_FREQ 12
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#define RB_ID_BOOTER 13
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#define RB_UART_SPEED_115200 0
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@ -71,6 +72,13 @@
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#define RB_BOOT_PROTOCOL_BOOTP 0
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#define RB_BOOT_PROTOCOL_DHCP 1
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#define RB_CPU_FREQ_L2 (0 << 3)
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#define RB_CPU_FREQ_L1 (1 << 3)
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#define RB_CPU_FREQ_N0 (2 << 3)
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#define RB_CPU_FREQ_H1 (3 << 3)
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#define RB_CPU_FREQ_H2 (4 << 3)
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#define RB_CPU_FREQ_H3 (5 << 3)
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#define RB_BOOTER_REGULAR 0
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#define RB_BOOTER_BACKUP 1
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