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ipq40xx: 5:15: refresh patches
- Drop upstream patch - Refresh dts patch Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
This commit is contained in:
Ansuel Smith
Sungbo Eo
parent
87318eb179
commit
29e177e4ee
@ -1,99 +0,0 @@
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From b8afc254b40167fd37b4d4263e750dab1f9ef157 Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Wed, 9 Sep 2020 18:38:31 +0200
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Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes
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Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.
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Signed-off-by: John Crispin <john@phrozen.org>
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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Cc: Luka Perkov <luka.perkov@sartura.hr>
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Reviewed-by: Vinod Koul <vkoul@kernel.org>
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Link: https://lore.kernel.org/r/20200909163831.1894142-1-robert.marko@sartura.hr
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
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1 file changed, 74 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -605,5 +605,79 @@
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reg = <4>;
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};
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};
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+
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+ usb3_ss_phy: ssphy@9a000 {
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+ compatible = "qcom,usb-ss-ipq4019-phy";
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+ #phy-cells = <0>;
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+ reg = <0x9a000 0x800>;
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+ reg-names = "phy_base";
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+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
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+ reset-names = "por_rst";
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+ status = "disabled";
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+ };
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+
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+ usb3_hs_phy: hsphy@a6000 {
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+ compatible = "qcom,usb-hs-ipq4019-phy";
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+ #phy-cells = <0>;
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+ reg = <0xa6000 0x40>;
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+ reg-names = "phy_base";
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+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
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+ reset-names = "por_rst", "srif_rst";
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+ status = "disabled";
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+ };
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+
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+ usb3: usb3@8af8800 {
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+ compatible = "qcom,dwc3";
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+ reg = <0x8af8800 0x100>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
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+ <&gcc GCC_USB3_SLEEP_CLK>,
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+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
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+ clock-names = "master", "sleep", "mock_utmi";
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+ ranges;
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+ status = "disabled";
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+
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+ dwc3@8a00000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x8a00000 0xf8000>;
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+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ dr_mode = "host";
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+ };
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+ };
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+
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+ usb2_hs_phy: hsphy@a8000 {
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+ compatible = "qcom,usb-hs-ipq4019-phy";
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+ #phy-cells = <0>;
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+ reg = <0xa8000 0x40>;
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+ reg-names = "phy_base";
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+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
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+ reset-names = "por_rst", "srif_rst";
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+ status = "disabled";
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+ };
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+
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+ usb2: usb2@60f8800 {
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+ compatible = "qcom,dwc3";
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+ reg = <0x60f8800 0x100>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
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+ <&gcc GCC_USB2_SLEEP_CLK>,
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+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
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+ clock-names = "master", "sleep", "mock_utmi";
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+ ranges;
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+ status = "disabled";
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+
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+ dwc3@6000000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x6000000 0xf8000>;
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+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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+ phys = <&usb2_hs_phy>;
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+ phy-names = "usb2-phy";
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+ dr_mode = "host";
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+ };
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+ };
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};
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};
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@ -1,44 +0,0 @@
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From d1ae4c808e7802008225078d93fbadd4aeea1e2d Mon Sep 17 00:00:00 2001
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From: Robert Marko <robert.marko@sartura.hr>
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Date: Wed, 9 Sep 2020 21:56:37 +0200
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Subject: [PATCH] ARM: dts: qcom: ipq4019: add more labels
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Lets add labels to more commonly used nodes for easier modification in board DTS files.
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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Cc: Luka Perkov <luka.perkov@sartura.hr>
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Link: https://lore.kernel.org/r/20200909195640.3127341-2-robert.marko@sartura.hr
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -190,7 +190,7 @@
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reg = <0x1800000 0x60000>;
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};
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- rng@22000 {
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+ prng: rng@22000 {
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compatible = "qcom,prng";
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reg = <0x22000 0x140>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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@@ -300,7 +300,7 @@
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status = "disabled";
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};
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- crypto@8e3a000 {
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+ crypto: crypto@8e3a000 {
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compatible = "qcom,crypto-v5.1";
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reg = <0x08e3a000 0x6000>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
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@@ -386,7 +386,7 @@
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dma-names = "rx", "tx";
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};
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- watchdog@b017000 {
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+ watchdog: watchdog@b017000 {
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compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
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reg = <0xb017000 0x40>;
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clocks = <&sleep_clk>;
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@ -1,35 +0,0 @@
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From e14775aa2feac18e7378cb8009b55c13d4236b50 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robert.marko@sartura.hr>
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Date: Mon, 7 Sep 2020 12:19:37 +0200
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Subject: [PATCH] ARM: dts: qcom: ipq4019: add SDHCI VQMMC LDO node
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Since we now have driver for the SDHCI VQMMC LDO needed
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for I/0 voltage levels lets introduce the necessary node for it.
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Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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Cc: Luka Perkov <luka.perkov@sartura.hr>
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Link: https://lore.kernel.org/r/20200907101937.10155-1-robert.marko@sartura.hr
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++
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1 file changed, 10 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -209,6 +209,16 @@
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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};
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+ vqmmc: regulator@1948000 {
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+ compatible = "qcom,vqmmc-ipq4019-regulator";
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+ reg = <0x01948000 0x4>;
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+ regulator-name = "vqmmc";
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+ regulator-min-microvolt = <1500000>;
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+ regulator-max-microvolt = <3000000>;
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+ regulator-always-on;
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+ status = "disabled";
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+ };
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+
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sdhci: sdhci@7824900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0x7824900 0x11c>, <0x7824000 0x800>;
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@ -10,10 +10,10 @@ Signed-off-by: John Crispin <john@phrozen.org>
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -903,11 +903,76 @@ dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-apq8074-dragonboard.dtb \
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qcom-apq8084-ifc6540.dtb \
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qcom-apq8084-mtp.dtb \
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@@ -902,11 +902,65 @@ dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-ipq4018-ap120c-ac.dtb \
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qcom-ipq4018-ap120c-ac-bit.dtb \
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qcom-ipq4018-jalapeno.dtb \
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+ qcom-ipq4018-a42.dtb \
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+ qcom-ipq4018-ap120c-ac.dtb \
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+ qcom-ipq4018-dap-2610.dtb \
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@ -29,7 +29,6 @@ Signed-off-by: John Crispin <john@phrozen.org>
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+ qcom-ipq4018-ex6150v2.dtb \
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+ qcom-ipq4018-fritzbox-4040.dtb \
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+ qcom-ipq4018-gl-ap1300.dtb \
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+ qcom-ipq4018-jalapeno.dtb \
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+ qcom-ipq4018-meshpoint-one.dtb \
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+ qcom-ipq4018-cap-ac.dtb \
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+ qcom-ipq4018-hap-ac2.dtb \
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