ipq40xx: net: phy: ar40xx: remove PHY handling
Since we now have proper PHY driver for the QCA807x PHY-s, lets remove PHY handling from AR40xx. This removes PHY driver, PHY GPIO driver and PHY init code. AR40xx still needs to handle PSGMII calibration as that requires R/W from the switch, so I am unable to move it into PHY driver. This also converted the AR40xx driver to use OF_MDIO to find the MDIO bus as it now cant be set through the PHY driver. So lets depend on OF_MDIO in KConfig. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This commit is contained in:
Robert Marko
Petr Štetiar
parent
b5c93edd74
commit
26b1f72381
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@ -25,6 +25,7 @@
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#include <linux/workqueue.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/of_mdio.h>
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#include <linux/mdio.h>
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#include <linux/gpio.h>
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@ -1245,42 +1246,6 @@ ar40xx_init_globals(struct ar40xx_priv *priv)
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ar40xx_write(priv, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), t);
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}
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static void
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ar40xx_malibu_init(struct ar40xx_priv *priv)
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{
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int i;
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struct mii_bus *bus;
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u16 val;
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bus = priv->mii_bus;
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/* war to enable AZ transmitting ability */
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ar40xx_phy_mmd_write(priv, AR40XX_PSGMII_ID, 1,
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AR40XX_MALIBU_PSGMII_MODE_CTRL,
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AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL);
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for (i = 0; i < AR40XX_NUM_PORTS - 1; i++) {
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/* change malibu control_dac */
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val = ar40xx_phy_mmd_read(priv, i, 7,
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AR40XX_MALIBU_PHY_MMD7_DAC_CTRL);
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val &= ~AR40XX_MALIBU_DAC_CTRL_MASK;
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val |= AR40XX_MALIBU_DAC_CTRL_VALUE;
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ar40xx_phy_mmd_write(priv, i, 7,
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AR40XX_MALIBU_PHY_MMD7_DAC_CTRL, val);
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if (i == AR40XX_MALIBU_PHY_LAST_ADDR) {
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/* to avoid goes into hibernation */
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val = ar40xx_phy_mmd_read(priv, i, 3,
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AR40XX_MALIBU_PHY_RLP_CTRL);
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val &= (~(1<<1));
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ar40xx_phy_mmd_write(priv, i, 3,
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AR40XX_MALIBU_PHY_RLP_CTRL, val);
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}
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}
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/* adjust psgmii serdes tx amp */
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mdiobus_write(bus, AR40XX_PSGMII_ID, AR40XX_PSGMII_TX_DRIVER_1_CTRL,
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AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP);
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}
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static int
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ar40xx_hw_init(struct ar40xx_priv *priv)
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{
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@ -1288,9 +1253,7 @@ ar40xx_hw_init(struct ar40xx_priv *priv)
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ar40xx_ess_reset(priv);
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if (priv->mii_bus)
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ar40xx_malibu_init(priv);
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else
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if (!priv->mii_bus)
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return -1;
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ar40xx_psgmii_self_test(priv);
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@ -1763,183 +1726,13 @@ static const struct switch_dev_ops ar40xx_sw_ops = {
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.get_port_link = ar40xx_sw_get_port_link,
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};
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/* Start of phy driver support */
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static const u32 ar40xx_phy_ids[] = {
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0x004dd0b1,
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0x004dd0b2, /* AR40xx */
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};
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static bool
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ar40xx_phy_match(u32 phy_id)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ar40xx_phy_ids); i++)
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if (phy_id == ar40xx_phy_ids[i])
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return true;
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return false;
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}
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static bool
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is_ar40xx_phy(struct mii_bus *bus)
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{
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unsigned i;
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for (i = 0; i < 4; i++) {
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u32 phy_id;
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phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
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phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
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if (!ar40xx_phy_match(phy_id))
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return false;
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}
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return true;
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}
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static int
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ar40xx_phy_probe(struct phy_device *phydev)
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{
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if (!is_ar40xx_phy(phydev->mdio.bus))
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return -ENODEV;
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ar40xx_priv->mii_bus = phydev->mdio.bus;
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phydev->priv = ar40xx_priv;
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if (phydev->mdio.addr == 0)
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ar40xx_priv->phy = phydev;
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linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported);
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linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->advertising);
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return 0;
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}
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static void
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ar40xx_phy_remove(struct phy_device *phydev)
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{
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ar40xx_priv->mii_bus = NULL;
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phydev->priv = NULL;
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}
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static int
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ar40xx_phy_config_init(struct phy_device *phydev)
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{
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return 0;
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}
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static int
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ar40xx_phy_read_status(struct phy_device *phydev)
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{
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if (phydev->mdio.addr != 0)
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return genphy_read_status(phydev);
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return 0;
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}
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static int
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ar40xx_phy_config_aneg(struct phy_device *phydev)
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{
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if (phydev->mdio.addr == 0)
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return 0;
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return genphy_config_aneg(phydev);
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}
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static struct phy_driver ar40xx_phy_driver = {
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.phy_id = 0x004d0000,
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.name = "QCA Malibu",
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.phy_id_mask = 0xffff0000,
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.features = PHY_GBIT_FEATURES,
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.probe = ar40xx_phy_probe,
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.remove = ar40xx_phy_remove,
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.config_init = ar40xx_phy_config_init,
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.config_aneg = ar40xx_phy_config_aneg,
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.read_status = ar40xx_phy_read_status,
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};
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static uint16_t ar40xx_gpio_get_phy(unsigned int offset)
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{
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return offset / 4;
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}
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static uint16_t ar40xx_gpio_get_reg(unsigned int offset)
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{
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return 0x8074 + offset % 4;
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}
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static void ar40xx_gpio_set(struct gpio_chip *gc, unsigned int offset,
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int value)
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{
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struct ar40xx_priv *priv = gpiochip_get_data(gc);
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ar40xx_phy_mmd_write(priv, ar40xx_gpio_get_phy(offset), 0x7,
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ar40xx_gpio_get_reg(offset),
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value ? 0xA000 : 0x8000);
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}
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static int ar40xx_gpio_get(struct gpio_chip *gc, unsigned offset)
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{
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struct ar40xx_priv *priv = gpiochip_get_data(gc);
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return ar40xx_phy_mmd_read(priv, ar40xx_gpio_get_phy(offset), 0x7,
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ar40xx_gpio_get_reg(offset)) == 0xA000;
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}
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static int ar40xx_gpio_get_dir(struct gpio_chip *gc, unsigned offset)
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{
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return 0; /* only out direction */
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}
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static int ar40xx_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
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int value)
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{
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/*
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* the direction out value is used to set the initial value.
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* support of this function is required by leds-gpio.c
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*/
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ar40xx_gpio_set(gc, offset, value);
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return 0;
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}
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static void ar40xx_register_gpio(struct device *pdev,
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struct ar40xx_priv *priv,
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struct device_node *switch_node)
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{
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struct gpio_chip *gc;
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int err;
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gc = devm_kzalloc(pdev, sizeof(*gc), GFP_KERNEL);
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if (!gc)
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return;
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gc->label = "ar40xx_gpio",
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gc->base = -1,
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gc->ngpio = 5 /* mmd 0 - 4 */ * 4 /* 0x8074 - 0x8077 */,
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gc->parent = pdev;
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gc->owner = THIS_MODULE;
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gc->get_direction = ar40xx_gpio_get_dir;
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gc->direction_output = ar40xx_gpio_dir_out;
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gc->get = ar40xx_gpio_get;
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gc->set = ar40xx_gpio_set;
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gc->can_sleep = true;
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gc->label = priv->dev.name;
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gc->of_node = switch_node;
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err = devm_gpiochip_add_data(pdev, gc, priv);
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if (err != 0)
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dev_err(pdev, "Failed to register gpio %d.\n", err);
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}
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/* End of phy driver support */
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/* Platform driver probe function */
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static int ar40xx_probe(struct platform_device *pdev)
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{
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struct device_node *switch_node;
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struct device_node *psgmii_node;
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struct device_node *mdio_node;
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const __be32 *mac_mode;
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struct clk *ess_clk;
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struct switch_dev *swdev;
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@ -2010,12 +1803,6 @@ static int ar40xx_probe(struct platform_device *pdev)
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return -EIO;
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}
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ret = phy_driver_register(&ar40xx_phy_driver, THIS_MODULE);
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if (ret) {
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dev_err(&pdev->dev, "Failed to register ar40xx phy driver!\n");
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return -EIO;
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}
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mutex_init(&priv->reg_mutex);
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mutex_init(&priv->mib_lock);
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INIT_DELAYED_WORK(&priv->mib_work, ar40xx_mib_work_func);
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@ -2023,6 +1810,15 @@ static int ar40xx_probe(struct platform_device *pdev)
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/* register switch */
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swdev = &priv->dev;
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mdio_node = of_find_compatible_node(NULL, NULL, "qcom,ipq4019-mdio");
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if (!mdio_node) {
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dev_err(&pdev->dev, "Probe failed - Cannot find mdio node by phandle!\n");
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ret = -ENODEV;
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goto err_missing_phy;
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}
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priv->mii_bus = of_mdio_find_bus(mdio_node);
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if (priv->mii_bus == NULL) {
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dev_err(&pdev->dev, "Probe failed - Missing PHYs!\n");
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ret = -ENODEV;
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@ -2037,8 +1833,10 @@ static int ar40xx_probe(struct platform_device *pdev)
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swdev->ports = AR40XX_NUM_PORTS;
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swdev->ops = &ar40xx_sw_ops;
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ret = register_switch(swdev, NULL);
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if (ret)
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goto err_unregister_phy;
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if (ret < 0) {
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dev_err(&pdev->dev, "Switch registration failed!\n");
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return ret;
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}
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num_mibs = ARRAY_SIZE(ar40xx_mibs);
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len = priv->dev.ports * num_mibs *
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@ -2051,15 +1849,10 @@ static int ar40xx_probe(struct platform_device *pdev)
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ar40xx_start(priv);
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if (of_property_read_bool(switch_node, "gpio-controller"))
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ar40xx_register_gpio(&pdev->dev, ar40xx_priv, switch_node);
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return 0;
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err_unregister_switch:
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unregister_switch(&priv->dev);
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err_unregister_phy:
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phy_driver_unregister(&ar40xx_phy_driver);
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err_missing_phy:
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platform_set_drvdata(pdev, NULL);
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return ret;
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@ -2074,8 +1867,6 @@ static int ar40xx_remove(struct platform_device *pdev)
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unregister_switch(&priv->dev);
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phy_driver_unregister(&ar40xx_phy_driver);
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return 0;
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}
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@ -1,12 +1,12 @@
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--- a/drivers/net/phy/Kconfig
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+++ b/drivers/net/phy/Kconfig
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@@ -584,6 +584,13 @@ config MDIO_IPQ40XX
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This driver supports the MDIO interface found in Qualcomm
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Atheros ipq40xx Soc chip.
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@@ -584,6 +584,13 @@ config XILINX_GMII2RGMII
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the Reduced Gigabit Media Independent Interface(RGMII) between
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Ethernet physical media devices and the Gigabit Ethernet controller.
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+config AR40XX_PHY
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+ tristate "Driver for Qualcomm Atheros IPQ40XX switches"
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+ depends on HAS_IOMEM && OF
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+ depends on HAS_IOMEM && OF && OF_MDIO
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+ select SWCONFIG
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+ help
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+ This is the driver for Qualcomm Atheros IPQ40XX ESS switches.
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