ar71xx: add kernel support for the Sitecom WLR-8100 wireless router
- unsure about copyright message - based on AP136-010 Patchwork: http://patchwork.openwrt.org/patch/4147/ Signed-off-by: Dirk Neukirchen <dirkneukirchen@web.de> [juhosg: rename and refresh kernel patch] Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 38589
This commit is contained in:
Gabor Juhos
parent
f6638a8994
commit
22b5040c64
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@ -89,6 +89,7 @@ CONFIG_ATH79_MACH_UBNT=y
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CONFIG_ATH79_MACH_UBNT_XM=y
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CONFIG_ATH79_MACH_WHR_HP_G300N=y
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CONFIG_ATH79_MACH_WLAE_AG300N=y
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CONFIG_ATH79_MACH_WLR8100=y
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CONFIG_ATH79_MACH_WNDAP360=y
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CONFIG_ATH79_MACH_WNDR3700=y
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CONFIG_ATH79_MACH_WNDR4300=y
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@ -0,0 +1,222 @@
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/*
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* Sitecom X8 AC1750 WLR-8100 board support
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*
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* Based on the Qualcomm Atheros AP135/AP136 reference board support code
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* Copyright (c) 2012 Qualcomm Atheros
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* Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include <linux/platform_device.h>
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#include <linux/ar8216_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "pci.h"
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#include "dev-ap9x-pci.h"
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#include "dev-gpio-buttons.h"
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#include "dev-eth.h"
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#include "dev-leds-gpio.h"
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#include "dev-m25p80.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#define WLR8100_GPIO_LED_USB 4
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#define WLR8100_GPIO_LED_WLAN_5G 12
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#define WLR8100_GPIO_LED_WLAN_2G 13
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#define WLR8100_GPIO_LED_STATUS_RED 14
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#define WLR8100_GPIO_LED_WPS_RED 15
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#define WLR8100_GPIO_LED_STATUS_AMBER 19
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#define WLR8100_GPIO_LED_WPS_GREEN 20
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#define WLR8100_GPIO_BTN_WPS 16
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#define WLR8100_GPIO_BTN_RFKILL 21
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#define WLR8100_KEYS_POLL_INTERVAL 20 /* msecs */
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#define WLR8100_KEYS_DEBOUNCE_INTERVAL (3 * WLR8100_KEYS_POLL_INTERVAL)
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#define WLR8100_MAC0_OFFSET 0
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#define WLR8100_MAC1_OFFSET 6
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#define WLR8100_WMAC_CALDATA_OFFSET 0x1000
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#define WLR8100_PCIE_CALDATA_OFFSET 0x5000
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static struct gpio_led wlr8100_leds_gpio[] __initdata = {
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{
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.name = "wlr8100:amber:status",
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.gpio = WLR8100_GPIO_LED_STATUS_AMBER,
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.active_low = 1,
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},
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{
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.name = "wlr8100:red:status",
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.gpio = WLR8100_GPIO_LED_STATUS_RED,
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.active_low = 1,
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},
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{
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.name = "wlr8100:green:wps",
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.gpio = WLR8100_GPIO_LED_WPS_GREEN,
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.active_low = 1,
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},
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{
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.name = "wlr8100:red:wps",
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.gpio = WLR8100_GPIO_LED_WPS_RED,
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.active_low = 1,
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},
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{
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.name = "wlr8100:red:wlan-2g",
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.gpio = WLR8100_GPIO_LED_WLAN_2G,
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.active_low = 1,
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},
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{
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.name = "wlr8100:red:usb",
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.gpio = WLR8100_GPIO_LED_USB,
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.active_low = 1,
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}
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};
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static struct gpio_keys_button wlr8100_gpio_keys[] __initdata = {
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{
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.desc = "WPS button",
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.type = EV_KEY,
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.code = KEY_WPS_BUTTON,
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.debounce_interval = WLR8100_KEYS_DEBOUNCE_INTERVAL,
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.gpio = WLR8100_GPIO_BTN_WPS,
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.active_low = 1,
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},
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{
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.desc = "RFKILL button",
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.type = EV_KEY,
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.code = KEY_RFKILL,
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.debounce_interval = WLR8100_KEYS_DEBOUNCE_INTERVAL,
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.gpio = WLR8100_GPIO_BTN_RFKILL,
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.active_low = 1,
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},
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};
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static struct ar8327_pad_cfg wlr8100_ar8327_pad0_cfg;
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static struct ar8327_pad_cfg wlr8100_ar8327_pad6_cfg;
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static struct ar8327_platform_data wlr8100_ar8327_data = {
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.pad0_cfg = &wlr8100_ar8327_pad0_cfg,
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.pad6_cfg = &wlr8100_ar8327_pad6_cfg,
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.port0_cfg = {
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.force_link = 1,
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.speed = AR8327_PORT_SPEED_1000,
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.duplex = 1,
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.txpause = 1,
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.rxpause = 1,
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},
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.port6_cfg = {
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.force_link = 1,
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.speed = AR8327_PORT_SPEED_1000,
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.duplex = 1,
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.txpause = 1,
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.rxpause = 1,
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},
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};
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static struct mdio_board_info wlr8100_mdio0_info[] = {
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{
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.bus_id = "ag71xx-mdio.0",
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.phy_addr = 0,
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.platform_data = &wlr8100_ar8327_data,
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},
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};
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static void __init wlr8100_gmac_setup(void)
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{
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void __iomem *base;
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u32 t;
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base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
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t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
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t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
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t |= QCA955X_ETH_CFG_RGMII_EN;
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__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
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iounmap(base);
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}
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static void __init wlr8100_common_setup(void)
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{
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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ath79_register_m25p80(NULL);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(wlr8100_leds_gpio),
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wlr8100_leds_gpio);
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ath79_register_gpio_keys_polled(-1, WLR8100_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(wlr8100_gpio_keys),
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wlr8100_gpio_keys);
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ath79_register_usb();
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ath79_register_wmac(art + WLR8100_WMAC_CALDATA_OFFSET, NULL);
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wlr8100_gmac_setup();
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ath79_register_mdio(0, 0x0);
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ath79_init_mac(ath79_eth0_data.mac_addr, art + WLR8100_MAC0_OFFSET, 0);
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mdiobus_register_board_info(wlr8100_mdio0_info,
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ARRAY_SIZE(wlr8100_mdio0_info));
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/* GMAC0 is connected to the RMGII interface */
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth0_data.phy_mask = BIT(0);
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ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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ath79_register_eth(0);
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/* GMAC1 is connected tot eh SGMII interface */
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ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
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ath79_eth1_data.speed = SPEED_1000;
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ath79_eth1_data.duplex = DUPLEX_FULL;
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ath79_register_eth(1);
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}
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static void __init wlr8100_010_setup(void)
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{
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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/* GMAC0 of the AR8337 switch is connected to GMAC0 via RGMII */
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wlr8100_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
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wlr8100_ar8327_pad0_cfg.txclk_delay_en = true;
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wlr8100_ar8327_pad0_cfg.rxclk_delay_en = true;
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wlr8100_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
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wlr8100_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
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/* GMAC6 of the AR8337 switch is connected to GMAC1 via SGMII */
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wlr8100_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
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wlr8100_ar8327_pad6_cfg.rxclk_delay_en = true;
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wlr8100_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
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ath79_eth0_pll_data.pll_1000 = 0xa6000000;
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ath79_eth1_pll_data.pll_1000 = 0x03000101;
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wlr8100_common_setup();
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ap91_pci_init(art + WLR8100_PCIE_CALDATA_OFFSET, NULL);
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}
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MIPS_MACHINE(ATH79_MACH_WLR8100, "WLR8100",
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"Sitecom WLR-8100",
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wlr8100_010_setup);
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@ -0,0 +1,39 @@
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -194,6 +194,16 @@ config ATH79_MACH_WLAE_AG300N
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select ATH79_DEV_LEDS_GPIO
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select ATH79_DEV_M25P80
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+config ATH79_MACH_WLR8100
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+ bool "Sitecom WLR-8100 board support"
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+ select SOC_QCA955X
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+ select ATH79_DEV_ETH
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+ select ATH79_DEV_GPIO_BUTTONS
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+ select ATH79_DEV_LEDS_GPIO
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+ select ATH79_DEV_SPI
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+ select ATH79_DEV_USB
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+ select ATH79_DEV_WMAC
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+
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config ATH79_MACH_WZR_HP_AG300H
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bool "Buffalo WZR-HP-AG300H board support"
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select SOC_AR71XX
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--- a/arch/mips/ath79/machtypes.h
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+++ b/arch/mips/ath79/machtypes.h
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@@ -128,6 +128,7 @@ enum ath79_mach_type {
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ATH79_MACH_WHR_HP_G300N, /* Buffalo WHR-HP-G300N */
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ATH79_MACH_WHR_HP_GN, /* Buffalo WHR-HP-GN */
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ATH79_MACH_WLAE_AG300N, /* Buffalo WLAE-AG300N */
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+ ATH79_MACH_WLR8100, /* SITECOM WLR-8100 */
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ATH79_MACH_WNDAP360, /* NETGEAR WNDAP360 */
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ATH79_MACH_WNDR3700, /* NETGEAR WNDR3700/WNDR3800/WNDRMAC */
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ATH79_MACH_WNDR4300, /* NETGEAR WNDR4300 */
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--- a/arch/mips/ath79/Makefile
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+++ b/arch/mips/ath79/Makefile
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@@ -104,6 +104,7 @@ obj-$(CONFIG_ATH79_MACH_UBNT) += mach-u
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obj-$(CONFIG_ATH79_MACH_UBNT_XM) += mach-ubnt-xm.o
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obj-$(CONFIG_ATH79_MACH_WHR_HP_G300N) += mach-whr-hp-g300n.o
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obj-$(CONFIG_ATH79_MACH_WLAE_AG300N) += mach-wlae-ag300n.o
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+obj-$(CONFIG_ATH79_MACH_WLR8100) += mach-wlr8100.o
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obj-$(CONFIG_ATH79_MACH_WNDAP360) += mach-wndap360.o
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obj-$(CONFIG_ATH79_MACH_WNDR3700) += mach-wndr3700.o
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obj-$(CONFIG_ATH79_MACH_WNDR4300) += mach-wndr4300.o
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