RepoMirrors/openwrt
1
0
Fork 0
mirror of git://git.openwrt.org/openwrt/openwrt.git synced 2024-12-26 00:22:47 +00:00
Code Issues Packages Projects Releases Wiki Activity

ramips: mt7628: fix memory controller reset bit

Browse Source 
According to MediaTek MT7688 Datasheet v1.4, as well as the MT7628
counterpart, the memory controller reset bit (MC_RST) is 10, not 20.
Reset bit 20 is used for for UART 2 (UART2_RST).

Please note: Due to the lack of hardware, I was not able to test this
change.

Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
This commit is contained in:
Reto Schneider 2021-06-11 11:19:51 +02:00 committed by Hauke Mehrtens
parent 577f3fdbc9
commit 2293f1abe4
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/linux/ramips/dts/mt7628an.dtsi
View File

@ -76,7 +76,7 @@
compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
reg = <0x300 0x100>;
resets = <&rstctrl 20>;
resets = <&rstctrl 10>;
reset-names = "mc";
interrupt-parent = <&intc>;